{"id":20578803,"url":"https://github.com/nrdmn/elbrus-docs","last_synced_at":"2025-08-19T02:42:44.694Z","repository":{"id":56289162,"uuid":"303447563","full_name":"nrdmn/elbrus-docs","owner":"nrdmn","description":null,"archived":false,"fork":false,"pushed_at":"2020-11-16T16:56:43.000Z","size":69,"stargazers_count":75,"open_issues_count":0,"forks_count":7,"subscribers_count":12,"default_branch":"master","last_synced_at":"2025-07-22T01:50:37.545Z","etag":null,"topics":["e2k","elbrus"],"latest_commit_sha":null,"homepage":"","language":"Assembly","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/nrdmn.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-10-12T16:18:26.000Z","updated_at":"2025-07-19T18:16:28.000Z","dependencies_parsed_at":"2022-08-15T16:01:07.113Z","dependency_job_id":null,"html_url":"https://github.com/nrdmn/elbrus-docs","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/nrdmn/elbrus-docs","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nrdmn%2Felbrus-docs","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nrdmn%2Felbrus-docs/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nrdmn%2Felbrus-docs/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nrdmn%2Felbrus-docs/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/nrdmn","download_url":"https://codeload.github.com/nrdmn/elbrus-docs/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nrdmn%2Felbrus-docs/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":271092128,"owners_count":24697903,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-08-19T02:00:09.176Z","response_time":63,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["e2k","elbrus"],"created_at":"2024-11-16T06:14:37.595Z","updated_at":"2025-08-19T02:42:44.633Z","avatar_url":"https://github.com/nrdmn.png","language":"Assembly","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Elbrus architecture\n\n\n## Overview\n\nElbrus 2000 (Elbrus or e2k for short), is a SPARC-inspired VLIW architecture\ndeveloped by the [Moscow Center for SPARC Technology (MCST)](http://mcst.ru/).\n\nElbrus machine code is organized into [very long instruction words (VLIW)](https://en.wikipedia.org/wiki/Very_long_instruction_word),\nwhich consist of multiple so-called syllables that are executed together.\n\n### References\n\nSeveral useful documents about Elbrus are available on the internet, albeit\nmostly in Russian.\n\n- [Руководство по эффективному программированию на платформе «Эльбрус» (elbrus-prog)](http://ftp.altlinux.org/pub/people/mike/elbrus/docs/elbrus_prog/html/)\n- [Микропроцессоры и вычислительные комплексы семейства «Эльбрус»](http://www.mcst.ru/doc/book_121130.pdf)\n- A series of articles about porting [Embox](https://www.embox.rocks/) to Elbrus:\n  [introduction](https://habr.com/ru/company/embox/blog/421441/),\n  [part 1](https://habr.com/ru/company/embox/blog/447704/),\n  [part 2](https://habr.com/ru/company/embox/blog/447744/),\n  [part 3](https://habr.com/ru/company/embox/blog/485694/)\n- Pictures of [various](https://www.zvezdasp.ru/products/vychislitelnyy-kompleks-elbrus) [Elbrus](https://www.zvezdasp.ru/products/kompyutery-serii-elbrus)\n  [mainboards](https://www.zvezdasp.ru/products/moduli-protsessornye)\n\n\n## Memory organization\n\nMost operations in Elbrus code either:\n\n- Take the values of one or more registers, compute a function, and write the\n  result to another register, or\n- Load a value from memory into a register or store a value from a\n  register into memory.\n\n\n### Register file, RF (Регистровый файл , РгФ)\n\nThe 256 general-purpose registers of the Register File (RF/РгФ) are divided\ninto two categories:\n\n- 224 registers are part of the _procedure stack_ in a\n  [windowed](https://en.wikipedia.org/wiki/Register_window) way. They can\n  become available or unavailable during procedure calls and returns.\n  (See also [elbrus-prog chapter 9.3.1.1](http://ftp.altlinux.org/pub/people/mike/elbrus/docs/elbrus_prog/html/chapter9.html#mech-register-window))\n- 32 registers are global registers. They are available during the whole\n  runtime of a program.\n\n 32-bit | 64-bit | description\n--------|--------|-----------------------------------\n `%g0`  |`%dg0`  | Global register (0-31)\n `%r0`  |`%dr0`  | Procedure stack register, relative to start of current window\n `%b[0]`|`%db[0]`| [Mobile base registers](http://ftp.altlinux.org/pub/people/mike/elbrus/docs/elbrus_prog/html/chapter9.html#baseregisters), relative to the start of the current window, plus `BR`\n\nTODO: last eight global registers are designated rotatable area\n\n\n#### Changing the register window\n\nThe procedure stack contains parameters and local data of procedures. Its top\narea is stored in the register file (RF). On overflow or underflow of the\nregister file, its contents are automatically swapped in/out of memory. Launch\nof a new procedure allocates a window on the procedure stack, which may overlap\nwith the calling procedure's window.\n\n\n### Procedure chain stack (стек связующей информации)\n\nStack of return addresses. It can only be manipulated by the operating system\nand the hardware. Its top area is stored in CF (chain file) registers.\n\nOn this stack the following information is encoded in two quad words:\n- return address\n- compilation unit index descriptor (CUIR)\n- window base (wbs) in the register file\n- presence of real 80 (?)\n- predicate file\n- user stack descriptor\n- rotatable area base\n- processor status register\n\nOn overflow or underflow of the chain file, its contents are automatically\nswapped in/out of memory.\n\n\n### Predicate file, PF (Предикатный файл, ПФ)\n\nComparison operations produce one-bit results (true or false) that can be\nstored in the predicate registers.\n\nPredicates can be used in conditional control transfers (jumps/calls), or in\nthe conditional execution of individual operations.\n\nThere are 32 predicate registers in the predicate file, which appear as\n`%pred0` to `%pred31` in assembly code.\n\n\n### Special purpose registers\n\nSpecial purpose registers can be read using the `rrs` and `rrd` operations, and\nwriting using the `rws` and `rwd` operations.\n\n Name   | Description\n--------|--------------------------------------------------------------\n CUIR   | compilation unit index register, индекс дескрипторов модуля компиляции\n PSHTP  | procedure stack hardware top pointer\n PSP    | procedure stack pointer - contains the virtual base address of the procedure stack.\n WD     | window descriptor - contains the base and the size of the current procedure's window into the procedure stack.\n PCSHTP | procedure chain stack hardware top pointer\n USBR   | user stack base pointer, РгБСП\n USD    | user stack descriptor, ДСП\n\n\n## Regular Instructions\n\nElbrus' wide instructions (широкая команда, ШК) are comprised of a header syllable and zero or more additional syllables. Wide instructions are 8 byte aligned and up to 16 words (64 bytes) long.\n\n### Syllables\n\nAbbreviation | Description\n-------------|---------------------------------------------------------\nHS           | Header syllable - it encodes length and structure of a wide instruction\nSS           | Stubs syllable - short operations that take only a few bits to encode\nALS          | Arithmetic logic channel syllable\nCS           | Control syllable\nALES         | Arithmetic logic extension channel semi-syllable. They extend corresponding ALS. ALES2 and ALES5 are only available on Elbrus v4 and higher.\nAAS          | Array access semi-syllable\nLTS          | Literal syllable - literals to be used as operands\nPLS          | Predicate logic syllable - processing of boolean values\nCDS          | Conditional syllable - specified which operations are to be executed under which condition\n\nThe first syllable is the header syllable. It is always present.\nPresence of other syllables depend on the purpose of the command.\nSyllables occur in the following order:\n\n- HS\n- SS\n- ALS0, ALS1, ALS2, ALS3, ALS4, ALS5\n- CS0\n- ALES2, ALES5\n- CS1\n- ALES0, ALES1, ALES3, ALES4\n- AAS0, AAS1, AAS2, AAS3, AAS4, AAS5\n- LTS3, LTS2, LTS1, LTS0\n- PLS2, PLS1, PLS0\n- CDS2, CDS1, CDS0\n\n#### Syllable packing\n\nSemi-syllables ALES and AAS are a half-word (2 bytes) long. All other syllables are one word (4 bytes) long.\n\nSyllables SS, ALS\\* and CS0 occur as indicated in the header syllable in the order described above.\nThey are packed, e.g. if header bits indicate presence of ALS0 and ALS2 but not SS nor ALS1, then the syllable ALS0 follows directly after HS and ALS2 follows directly after ALS0.\n\nIf presence of ALES2 or ALES5 is indicated, then a whole word is allocated for them, whether both are present or not.\nThe first of both to be present occupies the more significant half of the word, the second is encoded in the less significant half.\nFor example, when looking at the syllables as bytes, if ALES2 and ALES5 are present, then the first two bytes of the little endian word contain ALES5 and the last two bytes contain ALES2.\nIf only ALES5 is present, the first two bytes are empty and the last two bytes contain ALES5.\n\nCS1 may follow right after the previously described syllables.\n\nALES{0,1,3,4} and AAS\\* start at the word indicated by the \"middle pointer\" from the header syllable. Their ordering is the same as for ALES2 and ALES5 (high half first, low half second) but they are all packed. This means that any two syllables of ALES{0,1,3,4} and AAS{0,1} may share a word. ALES\\* may not share a word with AAS{2,3,4,5} because presence of the latter implies presence of AAS0 and/or AAS1.\nFor example, if ALES0, ALES1, ALES4, AAS0 and AAS2 are indicated, then they are encoded as ALES1, ALES0, AAS0, ALES4, two bytes left empty, and finally AAS2.\n\nLTS\\*, PLS\\* and CDS\\* are decoded starting from the end of the wide command.\nCDS\\* and PLS\\* are not indicated by individual flags but rather by their number. For example, there cannot be a PLS2 without a PLS0 and PLS1.\nLTS take any remaining words between the other syllables. For example, if after the AAS there are five words remaining in the wide command and two CDS and one PLS are indicated, then two words for LTS are left. They would be encoded as LTS1, LTS0, PLS0, CDS1, CDS0.\n\nWe do not know what happens if more syllables are indicated than there is space allocated or if syllables are encoded to overlap.\n\n#### HS - Header syllable\n\nBit     | Name          | Description\n------- | ------------- | -----------------------------------------------------\n   31   | ALS5          | arithmetic-logic syllable 5 presence\n   30   | ALS4          | arithmetic-logic syllable 4 presence\n   29   | ALS3          | arithmetic-logic syllable 3 presence\n   28   | ALS2          | arithmetic-logic syllable 2 presence\n   27   | ALS1          | arithmetic-logic syllable 1 presence\n   26   | ALS0          | arithmetic-logic syllable 0 presence\n   25   | ALES5         | arithmetic-logic extension syllable 5 presence\n   24   | ALES4         | arithmetic-logic extension syllable 4 presence\n   23   | ALES3         | arithmetic-logic extension syllable 3 presence\n   22   | ALES2         | arithmetic-logic extension syllable 2 presence\n   21   | ALES1         | arithmetic-logic extension syllable 1 presence\n   20   | ALES0         | arithmetic-logic extension syllable 0 presence\n 19:18  | PLS           | number of predicate logic syllables\n 17:16  | CDS           | number of conditional execution syllables\n   15   | CS1           | control syllable 1 presence\n   14   | CS0           | control syllable 0 presence\n   13   | set\\_mark     |\n   12   | SS            | stub syllable presence\n   11   | --            | unused\n   10   | loop\\_mode    |\n   9:7  | nop           |\n   6:4  |               | Length of instruction, in multiples of 8 bytes, minus 8 bytes\n   3:0  |               | Number of words occupied by SS, ALS, CS, ALES2, ALES5 - called \"middle pointer\"\n\n#### SS - Stubs syllable\n\n##### Stubs syllable format 1 - SF1\n\nBit     | Name     | Description\n--------|----------|----------------------------------------------\n 31:30  | ipd      | instruction prefetch depth\n   29   | eap      | end array prefetch\n   28   | bap      | begin array prefetch\n   27   | srp      |\n   26   | vfdi     |\n   25   | crp (?)  |\n   24   | abgi     |\n   23   | abgd     |\n   22   | abnf     |\n   21   | abnt     |\n   20   | type     | type is 0 for SF1\n   19   | abpf     |\n   18   | abpt     |\n   17   | alcf     |\n   16   | alct     |\n   15   |          | array access syllable 0 and 2 presence\n   14   |          | array access syllable 0 and 3 presence\n   13   |          | array access syllable 1 and 4 presence\n   12   |          | array access syllable 1 and 5 presence\n 11:10  | ctop     | `ctpr` number used in control transfer (`ct`) instructions\n   9    | ?        |\n   8:0  | ctcond   | condition code for control transfers (`ct`)\n\n##### Stubs syllable format 2 - SF2\n\nBit     | Name     | Description\n--------|----------|----------------------------------------------\n 31:30  | ipd      | instruction prefetch depth\n 29:28  |          | encodes invts and flushts, see below\n   27   | srp (?)  |\n   26   |          | encodes invts and flushts, see below\n   25   | crp (?)  |\n   20   | type     | type is 1 for SF2\n  4:0   | pred     | `pred` num\n\n`(ss \u003e\u003e 27 \u0026 6) \\| (ss \u003e\u003e 26 \u0026 1)`   | Description\n-----------------------------------|------------\n 2 | `invts`\n 3 | `flushts`\n 6 | `invts ? %predN`\n 7 | `invts ? ~ %predN`\n\n\n##### `ct` condition codes\n\nThe condition code in the stubs syllable controls under which conditions a\ncontrol transfer operation is executed.\n\n Bit    | description\n--------|--------------------------------------------------------------\n  4:0   | Predicate number (from `pred0` to `pred31`)\n  8:5   | Condition type\n\n Type |  syntax                       | description\n------|-------------------------------|---------------------------------\n   0  | --                            | never\n   1  |                               | always\n   2  | `? %pred0`                    | if predicate is true\n   3  | `? ~ %pred0`                  | if predicate is false\n   4  | `? #LOOP_END`                 |\n   5  | `? #NOT_LOOP_END`             |\n   6  | `? %pred0 \\|\\| #LOOP_END`     |\n   7  | `? ~ %pred0 \u0026\u0026 #NOT_LOOP_END` |\n   8  | (TODO, depends on syllable)   |\n   9  | (TODO, depends on syllable)   |\n  10  | (reserved)                    |\n  11  | (reserved)                    |\n  12  | (reserved)                    |\n  13  | (reserved)                    |\n  14  | `? ~ %pred0 \\|\\| #LOOP_END`   |\n  15  | `? %pred0 \u0026\u0026 #NOT_LOOP_END`   |\n\n`#LOOP_END` and `#NOT_LOOP_END` are sometimes spelled as `%LOOP_END` and `%NOT_LOOP_END`.\n\n#### ALS - Arithmetic-logical syllables\n\nBit     | Description\n------- | -------------------------------------------------------------\n   31   | Speculative mode\n 30:24  | Opcode\n 23:16  | Operand src1, or opcode extension\n 15:8   | Operand src2\n  7:0   | Operand src3, dst, or cmp opcode extension\n\nSee chapter 'Arithmetic-logical operations' for more information on the operands.\n\n#### ALES - Arithmetic-logical extension syllables\n\nBit     | Description\n------- | -------------------------------------------------------------\n  15:8  | Opcode2\n   7:0  | src3 (in ALEF1) or opcode extension 2 or cmp opcode extension (in ALEF2)\n\n#### CS - Control syllables\n\nCS0 and CS1 encode different operations.\n\n Syllable | pattern   | name   | description\n----------|-----------|--------|----------------------------------------\n CS0, CS1 |`0xxxxxxx` | set\\*  | setwd/setbn/setbp/settr\n CS1      |`1xxxxxxx` | vrfpsz | vrfpsz + setwd/setbn/setbp/settr\n CS0      |`2xxxxxxx` | puttsd | puttsd with a multiple-of-8 parameter relative to the start of the current instruction\n CS1      |`200000xx` | setei  |\n CS1      |`28000000` | setsft |\n CS0, CS1 |`300000xx` | wait   | wait for specified kinds of operations to complete\n CS0      |`4xxxxxxx` | disp   | prepare a relative jump in `ctpr1`\n CS0      |`5xxxxxxx` | ldisp  | prepare an array prefetch program (?) in `ctpr1`\n CS0      |`6xxxxxxx` | sdisp  | prepare a system call in `ctpr1`\n CS0      |`70000000` | return | prepare to return from procedure in `ctpr1`\n CS0      |`8xxxxxxx+`| --     | disp/ldisp/sdisp/return with ctpr2\n CS0      |`cxxxxxxx+`| --     | disp/ldisp/sdisp/return with ctpr3\n CS1      |`6xxxx000` | setmas | Set memory address specifier for load and store operations\n\n\n\n##### set\\*\n\nThe set\\* operation sets several parameters related to register windows.\nMost bits are encoded in the CS0 syllable itself, but some are also read from\nthe LTS0 syllable.\n\nAccording to `ldis`, setwd is always performed, but settr, setbn, and setbp\nhave to be enabled by setting the corrsponding bits in CS0.\n\n Syl. | bit    | name        | description\n------|--------|-------------|-----------------------------------------\n CS1  |     28 |enable vfrpsz|\n CS   |     27 |enable settr |\n CS   |     26 |enable setbn |\n CS   |     25 |enable setbp |\n CS   |  22:18 | setbp psz=x |\n CS   |  17:12 | setbn rcur=x|\n CS   |  11:6  | setbn rsz=x |\n CS   |   5:0  | setbn rbs=x |\n LTS0 |  16:12 |vfrpsz rpsz=x|\n LTS0 |  11:5  | setwd wsz=x |\n LTS0 |     4  | setwd nfx=x |\n LTS0 |     3  | setwd dbl=x |\n\n\n##### wait\n\n Bit    | name  | description\n--------|-------|------------------------------------------------------\n  5     |`ma_c` | wait for all previous memory access operations to complete\n  4     |`fl_c` | wait for all previous cache flush operations to complete\n  3     |`ls_c` | wait for all previous load operations to complete\n  2     |`st_c` | wait for all previous store operations to complete\n  1     |`all_e`| wait for all previous operations to issue all possible exceptions\n  0     |`all_c`| wait for all previous operations to complete\n\n##### disp/ldisp/sdisp/return\n\nThe `disp` operation prepares a jump to a different location by using one of\nthe control transfer preparation registers (`ctpr1` to `ctpr3`).\n\n bit    | description\n--------|--------------------------------------------------------------\n  31:30 | can be 1, 2, or 3 for `ctpr1`, `ctpr2`, or `ctpr3` respectively\n  29:28 | can be 0, 1, 2, or 3, for `disp`, `ldisp`, `sdisp`, or `return` respectively\n  27:0  | offset or system call number\n\nFor `disp` and `ldisp`, the offset is relative to the start of the current\ninstruction, and in multiples of eight bytes. For example, in an instruction at\n`0x1000`, with CS0=`40000042`, we get `disp %ctpr1, 0x1210`.\n\n`ldisp` is only allowed with `ctpr2`.\n\nFor `sdisp`, the system call number is not shifted. `CS0=6000001a` is\n`sdisp %ctpr1, 0x1a`.\n\nThe `return` operation doesn't take an offset. The offset field should be zero\nin this case.\n\n##### setmas (setting the memory address specifier)\n\n[Memory address specifiers](https://repo.or.cz/linux/elbrus.git/blob/HEAD:/arch/e2k/include/asm/mas.h)\ncontrol multiple aspects of load and store operations. Their 7-bit format is\ndescribed elsewhere.\n\nThe MAS can be independently specified for load and store operations, in CS1:\n\n CS1 bits | description\n----------|-------------------------------------------------------------\n  27:21   | MAS for load operations\n  20:14   | MAS for store operations\n\n\n## Array Prefetch Instructions\n\nArray prefetch instructions are run asynchronously on the array access unit.\nThey are always 16 bytes long.\nTo assemble array prefetch instructions, the mnemonic `fapb` is used.\nTo call an array prefetch program, load its address with ldisp to %ctpr2 (no need to call or ct).\nEven though array prefetch instructions should only ever be called by ldisp and are not processed using the same facilities as\nregular instructions, they always seem to be terminated by a regular branch instruction.\nThe maximum length of an array prefetch program is 32 instructions.\n\n\n\n## Arithmetic-logical operations\n\nALU operations are generally identified by several aspects:\n\n- The opcode field in the ALS\n- If a corrsponding ALES exists, the opcode2 field in the ALES\n- Opcode extension, opcode extension 2, and cmp opcode extension, depending on the opcode\n- The ALUs in which the operation can be performed. Sometimes the same opcode\n  can mean different operations in different ALUs (numbered from 0 to 5)\n\nThe format of an arithmetic-logical operation (ALOPF) is determined by opcode,\nchannel, and presence of an ALES. The presence and location of additional\nidentifying criteria of an operation as well as operands depend on the ALOPF.\n\nOther variations:\n- Some operations require two ALS\n- Some operations require a Memory Address Specifier (MAS) in CS1\n- Some operations have predicates. Some operations require additional data from CDS.\n- ALOPF1, ALOPF2, ALOPF3, ALOPF7, ALOPF8 require no ALES, all others seem to require an ALES.\n\n### Operands and other fields\n\n Field                | encoded in                                        | comment\n----------------------|---------------------------------------------------|------------------------------------------------------\n opcode               | `ales[30:24]`                                     |\n opcode2              | `ales[15:8]`                                      |\n opcode extension     | `als[23:16]`                                      |\n opcode extension 2   | `ales[7:0]`                                       |\n cmp opcode extension | `als[7:5]` or `ales[7:0]`                         |\n src1                 | `als[23:16]`                                      | source operand 1\n src2                 | `als[15:8]`                                       | source operand 2 - can encode access to literal syllables (LTS)\n src3                 | `als[7:0]` or `ales[7:0]`                         | source operand 3 - for ALOPF3 and ALOPF13 it is in ALS, for ALOPF21 it is in ALES\n dst                  | `als[7:0]`, or `als[4:0]` for predicate registers | destination register\n\n#### src1 encoding\n\nPattern   | Range | Description\n----------|-------|------------------------------------\n0xxx xxxx | 00-7f | Rotatable area procedure stack register\n10xx xxxx | 80-bf | procedure stack register\n110x xxxx | c0-df | constant between 0 and 31\n111x xxxx | e0-ff | global register\n\n#### src2 encoding\n\nsrc2 that are not status register numbers are encoded as follows:\n\nPattern   | Range        | Description\n----------|--------------|------------------------------------\n0xxx xxxx | 00-7f        | Rotatable area procedure stack register\n10xx xxxx | 80-bf        | procedure stack register\n1100 xxxx | c0-cf        | constant between 0 and 15\n1101 000x | d0-d1        | reference to 16 bit literal semi-syllable, low half of LTS0 or LTS1\n1101 010x | d4-d5        | reference to 16 bit literal semi-syllable, high half of LTS0 and LTS1\n1101 10xx | d8-db        | reference to 32 bit literal syllable LTS0, LTS1, LTS2, or LTS3\n1101 11xx | dc-de        | reference to 64 bit literal syllable pair LTS1:LTS0, LTS2:LTS1, or LTS3:LTS2\n111x xxxx | e0-ff        | global register\n\nLiteral half-syllables are sign-extended on access. Thus, values 0-0x7fff and\n0xffff8000-0xffffffff (-0x8000 to -1) can be encoded in a literal half-syllable.\n\n#### src3 encoding\n\nPattern   | Range | Description\n----------|-------|------------------------------------\n0xxx xxxx | 00-7f | Rotatable area procedure stack register\n10xx xxxx | 80-bf | procedure stack register\n111x xxxx | e0-ff | global register\n\n#### dst encoding\n\ndst that are not predicate register numbers or status register numbers are encoded as follows:\n\nPattern   | Range | Description\n----------|-------|------------------------------------\n0xxx xxxx | 00-7f | Rotatable area procedure stack register\n10xx xxxx | 80-bf | procedure stack register\n1100 1101 | cd    | %tst\n1100 1110 | ce    | %tc\n1100 1111 | cf    | %tcd\n1101 0001 | d1    | %ctpr1\n1101 0010 | d2    | %ctpr2\n1101 0011 | d3    | %ctpr3\n1101 1110 | de    | %empty.lo\n1101 1111 | df    | %empty.hi\n111x xxxx | e0-ff | global register\n\n#### opcode2 values\n\n Opcode2 | Name\n----------|-------------\n 0x01     | EXT\n 0x02     | EXT1\n 0x03     | EXT2\n 0x04     | FLB\n 0x05     | FLH\n 0x06     | FLW\n 0x07     | FLD\n 0x08     | ICMB0\n 0x09     | ICMB1\n 0x0a     | ICMB2\n 0x0b     | ICMB3\n 0x0c     | FCMB0\n 0x0d     | FCMB1\n 0x0e     | PFCMB0\n 0x0f     | PFCMB1\n 0x10     | LCMBD0\n 0x11     | LCMBD1\n 0x12     | LCMBQ0\n 0x13     | LCMBQ1\n 0x16     | QPFCMB0\n 0x17     | QPFCMB1\n\n\n### Arithmetic-logical operation formats (ALOPF)\n\nSeveral operand formats are defined.\n\n Format            | Has ALES? | src1 | src2 | src3        | dst | opcode ext   | opcode ext 2 | cmp opcode ext | Example            | Comment\n-------------------|-----------|------|------|-------------|-----|--------------|--------------|----------------|--------------------|---------------\n 1                 |           | x    | x    |             | x   |              |              |                | adds, ld{b,h,w,d}  |\n 2                 |           |      | x    |             | x   | x            |              |                | movx, popcnts      |\n 3                 |           | x    | x    | `als[7:0]`  |     |              |              |                | st{b,h,w,d}        |\n 7                 |           | x    | x    |             | x   |              |              | `als[7:5]`     | cmposb             | dst is a predicate register\n 8                 |           |      | x    |             | x   |              |              | `als[7:5]`     | cctopo             | dst is a predicate register\n 11                | x         | x    | x    |             | x   |              | x            |                | muls               |\n 11 (with literal) | x         | x    | x    |             | x   |              |              |                | psllqh             | These opcodes require a literal in `ales[7:0]`\n 12                | x         |      | x    |             | x   | x            | x            |                | fsqrts             | Opcode `pshufh` is special as it requires a literal in `ales[7:0]`.\n 13                | x         | x    | x    | `als[7:0]`  |     |              | x            |                | stq                |\n 15                | x         |      | x    |             | x   |              | x            |                | rws, rwd           | dst is a status register; opcode2 is EXT; opcode extension 2 is 0xc0\n 16                | x         | x    |      |             | x   |              | x            |                | rrs, rrd           | src2 is a status register; opcode2 is EXT; opcode extension 2 is 0xc0\n 17                | x         | x    | x    |             | x   |              |              | `ales[7:0]`    | pcmpeqbop          | dst is a predicate register; opcode2 is EXT1\n 21                | x         | x    | x    | `ales[7:0]` | x   |              |              |                | incs\\_fb           |\n 22                | x         |      | x    |             | x   | x            | x            |                | movtq              | opcode2 is EXT; ALES opcode extension is 0xc0\n\nFor the locations of operands where none is explicitly specified here, see table 'Operands and other fields'.\n\nTODO: ALOPF5, ALOPF6, ALOPF7, ALOPF9, ALOPF10, ALOPF19\n\nNOTE: ALOPF9 and ALOPF10 have a 16 bit opcode extension\n\n### List of operations\n\nThe following tables are grouped by opcode2 and sorted by opcode.\n\n#### Short operations (without ALES)\n\n Opcode | ALUs | name     | ALS[23:16]| ALS[15:8] | ALS[7:0]  | data width | description\n--------|------|----------|-----------|-----------|-----------|------------|--------------------------\n  0x00  | all  | ands     |  src1     |  src2     |  dst      | 32 bits    | Compute bit-wise AND of src1 and src2, store result in dst\n  0x01  | all  | andd     |  src1     |  src2     |  dst      | 64 bits    | Compute bit-wise AND of src1 and src2, store result in dst\n  0x10  | all  | adds     |  src1     |  src2     |  dst      | 32 bits    | Compute bit-wise AND of src1 and src2, store result in dst\n  0x11  | all  | addd     |  src1     |  src2     |  dst      | 64 bits    | Compute bit-wise AND of src1 and src2, store result in dst\n  0x24  | 25   | stb      |  src1     |  src2     |  src3     |  8 bits    | store  8-bit value from src3 to address at src1+src2\n  0x25  | 25   | sth      |  src1     |  src2     |  src3     | 16 bits    | store 16-bit value from src3 to address at src1+src2\n  0x26  | 25   | stw      |  src1     |  src2     |  src3     | 32 bits    | store 32-bit value from src3 to address at src1+src2\n  0x26  | 0134 | bitrevs  |  0xc0     |  src2     |  dst      | 32 bits    | \n  0x27  | 25   | std      |  src1     |  src2     |  src3     | 64 bits    | store 64-bit value from src3 to address at src1+src2\n  0x27  | 0134 | bitrevd  |  0xc0     |  src2     |  dst      | 64 bits    | \n  0x64  | 0235 | ldb      |  src1     |  src2     |  dst      |  8 bits    | load  8-bit value from address at src1+src2, store into dst\n  0x65  | 0235 | ldh      |  src1     |  src2     |  dst      | 16 bits    | load 16-bit value from address at src1+src2, store into dst\n  0x66  | 0235 | ldw      |  src1     |  src2     |  dst      | 32 bits    | load 32-bit value from address at src1+src2, store into dst\n  0x67  | 0235 | ldd      |  src1     |  src2     |  dst      | 64 bits    | load 64-bit value from address at src1+src2, store into dst\n\n\n#### EXT (opcode2 = 1)\n\n Opcode | ALUs | name     | ALS[23:16]| ALS[15:8] | ALS[7:0]  | ALES[7:0]  | data width | description\n--------|------|----------|-----------|-----------|-----------|------------|------------|-------------\n  0x58  | 0    | getsp    |  0xec     |  src2     |  dst      | unused     | 32 -\u003e 64   | Add src2 to user stack pointer, store in user stack pointer and dst\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnrdmn%2Felbrus-docs","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fnrdmn%2Felbrus-docs","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnrdmn%2Felbrus-docs/lists"}