{"id":13537130,"url":"https://github.com/nvdla/hw","last_synced_at":"2025-04-02T04:30:27.277Z","repository":{"id":41055376,"uuid":"104814568","full_name":"nvdla/hw","owner":"nvdla","description":"RTL, Cmodel, and testbench for NVDLA","archived":false,"fork":false,"pushed_at":"2022-03-02T14:10:39.000Z","size":20795,"stargazers_count":1738,"open_issues_count":200,"forks_count":568,"subscribers_count":167,"default_branch":"nvdlav1","last_synced_at":"2024-11-03T02:32:27.750Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/nvdla.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2017-09-26T00:08:46.000Z","updated_at":"2024-11-01T05:06:52.000Z","dependencies_parsed_at":"2022-08-10T01:42:03.706Z","dependency_job_id":null,"html_url":"https://github.com/nvdla/hw","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nvdla%2Fhw","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nvdla%2Fhw/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nvdla%2Fhw/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nvdla%2Fhw/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/nvdla","download_url":"https://codeload.github.com/nvdla/hw/tar.gz/refs/heads/nvdlav1","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246756728,"owners_count":20828752,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T09:00:55.408Z","updated_at":"2025-04-02T04:30:22.269Z","avatar_url":"https://github.com/nvdla.png","language":"Verilog","funding_links":[],"categories":["Accelerators","其他_机器学习与深度学习"],"sub_categories":[],"readme":"# NVDLA Open Source Hardware, version 1.0\n---\n\n## NVDLA\n\nThe NVIDIA Deep Learning Accelerator (NVDLA) is a free and open architecture that promotes\na standard way to design deep learning inference accelerators. With its modular architecture,\nNVDLA is scalable, highly configurable, and designed to simplify integration and portability.\nLearn more about NVDLA on the project web page.\n\n\u003chttp://nvdla.org/\u003e\n\n## About this release\n\nThis release, in the `nvdlav1` branch, contains the non-configurable\n\"full-precision\" version of NVDLA.  This non-configurable version is fixed\nat 2048 8-bit MACs (or 1024 16-bit fixed- or floating-point MACs).  This\nbranch is expected to be a stable sustaining release; although bug fixes may\nbe added, new RTL feature improvements will not appear in this branch. \nAdditionally, this branch will diverge from the `master` branch; commits\nfrom that branch may be cherry-picked into this branch, but wholesale merges\nfrom `master` will not appear on `nvdlav1`.\n\n## Online Documentation\n\nNVDLA documentation is located [here](http://nvdla.org/contents.html).  Hardware specific \ndocumentation is located at the following pages.\n* [Hardware Architecture](http://nvdla.org/hwarch.html).\n* [Integrator's Manual](http://nvdla.org/integration_guide.html).\n\nThis README file contains only basic information.\n\n## Directory Structure\n\nThis repository contains the RTL, C-model, and testbench code associated with the NVDLA hardware \nrelease.  In this repository, you will find:\n\n  * vmod/ -- RTL model, including:\n    * vmod/nvdla/ -- Verilog implementation of NVDLA\n    * vmod/vlibs/ -- library and cell models\n    * vmod/rams/ -- behavioral models of RAMs used by NVDLA\n  * syn/ -- example synthesis scripts for NVDLA\n  * perf/ -- performance estimator spreadsheet for NVDLA\n  * verif/ -- trace-player testbench for basic sanity validation\n    * verif/traces/ -- sample traces associated with various networks\n  * tools -- tools used for building the RTL and running simulation/synthesis/etc.\n  * spec -- RTL configuration option settings.\n\n## Building the NVDLA Hardware\n\nSee the [integrator's manual](http://nvdla.org/integration_guide.html) for more information on \nthe setup and other build commands and options.  The basic build command to compile the design\nand run a short sanity simulation is:\n\n    bin/tmake\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnvdla%2Fhw","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fnvdla%2Fhw","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fnvdla%2Fhw/lists"}