{"id":13417266,"url":"https://github.com/olofk/fusesoc","last_synced_at":"2025-05-13T21:07:16.753Z","repository":{"id":14256722,"uuid":"16964283","full_name":"olofk/fusesoc","owner":"olofk","description":"Package manager and build abstraction tool for FPGA/ASIC development","archived":false,"fork":false,"pushed_at":"2025-04-18T20:21:45.000Z","size":2581,"stargazers_count":1275,"open_issues_count":131,"forks_count":257,"subscribers_count":65,"default_branch":"main","last_synced_at":"2025-04-28T12:15:53.342Z","etag":null,"topics":["eda","fpga","package-manager","python","reuse","verilog","vhdl"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-2-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/olofk.png","metadata":{"files":{"readme":"README.md","changelog":"NEWS","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2014-02-18T21:27:06.000Z","updated_at":"2025-04-28T07:08:26.000Z","dependencies_parsed_at":"2024-03-08T20:47:36.556Z","dependency_job_id":"f9f1cebe-d24a-4489-a417-4514bea6e5cf","html_url":"https://github.com/olofk/fusesoc","commit_stats":{"total_commits":1484,"total_committers":75,"mean_commits":"19.786666666666665","dds":"0.48450134770889486","last_synced_commit":"48e949c9191212c322db04af3a90011855d0ac4f"},"previous_names":[],"tags_count":33,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/olofk%2Ffusesoc","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/olofk%2Ffusesoc/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/olofk%2Ffusesoc/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/olofk%2Ffusesoc/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/olofk","download_url":"https://codeload.github.com/olofk/fusesoc/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":251311334,"owners_count":21569009,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["eda","fpga","package-manager","python","reuse","verilog","vhdl"],"created_at":"2024-07-30T22:00:34.712Z","updated_at":"2025-04-28T12:16:01.439Z","avatar_url":"https://github.com/olofk.png","language":"Python","readme":"# FuseSoC\n\n[![CI status](https://github.com/olofk/fusesoc/workflows/CI/badge.svg)](https://github.com/olofk/fusesoc/actions?query=workflow%3ACI)\n[![image](https://img.shields.io/pypi/dm/fusesoc.svg?label=PyPI%20downloads)](https://pypi.org/project/fusesoc/)\n\n## Introduction\n\nFuseSoC is an award-winning package manager and a set of build tools for\nHDL (Hardware Description Language) code.\n\nIts main purpose is to increase reuse of IP (Intellectual Property)\ncores and be an aid for creating, building and simulating SoC solutions.\n\nFuseSoC makes it easier to\n\n-   reuse existing cores\n-   create compile-time or run-time configurations\n-   run regression tests against multiple simulators\n-   port designs to new targets\n-   let other projects use your code\n-   set up continuous integration\n\nTo learn more about FuseSoC head over to the\n[User Guide](https://fusesoc.readthedocs.io/en/stable/user).\n\n## Getting started\n\n### Installing the latest release\n\nFuseSoC works on Linux, Windows, and macOS. It is written in Python and can be\ninstalled like any other Python package through \"pip\". Please refer to the\nfull list of system requirements and installation instructions in the\n[Installation section in the User Guide](https://fusesoc.readthedocs.io/en/stable/user/installation.html).\n\n### Quick start\n\nTo check if FuseSoC is working, and to get an initial feeling for how FuseSoC\nworks, you can try to simulate a simple hardware design from our core library.\n\nFirst, create and enter an empty workspace\n\n    mkdir workspace\n    cd workspace\n\nInstall the FuseSoc base library into the workspace\n\n    fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores\n\nGet a list of cores found in the workspace\n\n    fusesoc core list\n\nIf you have any of the supported simulators installed, you can try to\nrun a simulation on one of the cores as well. For example,\n`fusesoc run --target=sim i2c` will run a regression test on the core\ni2c with Icarus Verilog. If you want to try another simulator instead,\nadd e.g. `--tool=modelsim` or `--tool=xcelium` between `run` and `i2c`.\n\n`fusesoc --help` will give you more information on commands and switches.\n\nDid it work? Great! FuseSoC can be used to create FPGA images, perform\nlinting, manage your IP libraries or do formal verification as well.\nCheck out the [online documentation](https://fusesoc.readthedocs.io/en/stable/)\nto learn more about creating your own core files and using\nexisting ones. If it didn't work, please get in touch (see below).\n\n## Next steps\n\nA good way to get your first hands-on experience with FuseSoC is to\ncontribute to the [LED to Believe](https://github.com/fusesoc/blinky)\nproject. This project aims to used FuseSoC to blink a LED on every\navailable FPGA development board in existence. There are already around\n40 different boards supported. If your board is already supported,\ngreat, then you can run your first FuseSoC-based design. If it's not\nsupported, great, you now have the chance to add it to the list of\nsupported boards. Either way, head over to [LED to\nBelieve](https://github.com/fusesoc/blinky) to learn more and see how to\ngo from a blinking LED to running a RISC-V core on an FPGA.\n\n## Need help?\n\nFuseSoC comes with extensive\n[online documentation](https://fusesoc.readthedocs.io/en/stable/index.html).\n\nFor quick communication with the active developers, feel free to join us at the\n[FuseSoC chat](https://gitter.im/librecores/fusesoc).\n\nIf you have found an issue, or want to know more about currently known problems,\ncheck out the\n[issue tracker on GitHub](https://github.com/olofk/fusesoc/issues).\n\nIf you are looking for professional paid support, we are happy to\nprovide feature additions, bug fixes, user training, setting up core\nlibraries, migrating existing designs to FuseSoC and other things.\nPlease contact \u003colof.kindgren@gmail.com\u003e for more information.\n\n## Contributing to FuseSoC\n\nFuseSoC is developed by an active and friendly community, and you're welcome to\njoin! You can read more about setting up a development environment in our\n[Developer's Guide](https://fusesoc.readthedocs.io/en/latest/dev/index.html).\n\nYou can file bug reports and propose changes in the [olofk/fusesoc repository on GitHub](https://github.com/olofk/fusesoc).\n\n## Further reading\n\n* A Scalable Approach to IP Management with FuseSoC [paper](https://osda.gitlab.io/19/kindgren.pdf) and [slides](https://osda.gitlab.io/19/kindgren-slides.pdf) from OSDA 2019\n* Antmicro blog post on [how to use FuseSoC as a linter](https://antmicro.com/blog/2020/04/systemverilog-linter-and-formatter-in-fusesoc/)\n* [FuseSoC-related posts on the Tales from Beyond the Register Map blog](https://blog.award-winning.me/search/label/FuseSoC)\n* [Presentation from RISC-V Week 2022](https://www.award-winning.me/fusesoc-rvweek22)\n* [Presentation from Latch-Up Portland 2019](https://www.youtube.com/watch?v=7eWRAOK9mns)\n* [Presentation from WOSH 2019](https://www.youtube.com/watch?v=HOFYplIBSWM)\n* [Presentation from ORConf 2017](https://www.youtube.com/watch?v=iPpT9k_H67k)\n* [Presentation from ORConf 2016](https://www.youtube.com/watch?v=pKlJWe_HKPM)\n\n## License\n\nFuseSoC is licensed under the permissive 2-clause BSD license, freely allowing\nuse, modification, and distribution of FuseSoC for all kinds of projects.\nPlease refer to the [LICENSE](LICENSE) file for details.\n","funding_links":[],"categories":["riscv-dv","Python","Operation System","Tools","FPGA Tools","Other Design Automation tools","Build Systems","Hardware Verification"],"sub_categories":["fsva","Embedded Operation System","Interfaces","Mesh networks","Tools"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Folofk%2Ffusesoc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Folofk%2Ffusesoc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Folofk%2Ffusesoc/lists"}