{"id":18429037,"url":"https://github.com/openhwgroup/core-v-mcu","last_synced_at":"2026-01-22T05:02:42.135Z","repository":{"id":37090624,"uuid":"274802727","full_name":"openhwgroup/core-v-mcu","owner":"openhwgroup","description":"This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.","archived":false,"fork":false,"pushed_at":"2025-10-02T22:38:46.000Z","size":38398,"stargazers_count":187,"open_issues_count":88,"forks_count":65,"subscribers_count":20,"default_branch":"master","last_synced_at":"2025-10-03T00:23:51.283Z","etag":null,"topics":["microcontroller","openhwgroup","riscv","systemverilog"],"latest_commit_sha":null,"homepage":"https://docs.openhwgroup.org/projects/core-v-mcu","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/openhwgroup.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":"CITATION.cff","codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2020-06-25T01:14:03.000Z","updated_at":"2025-10-02T22:38:50.000Z","dependencies_parsed_at":"2025-10-03T00:24:51.694Z","dependency_job_id":null,"html_url":"https://github.com/openhwgroup/core-v-mcu","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/openhwgroup/core-v-mcu","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcore-v-mcu","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcore-v-mcu/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcore-v-mcu/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcore-v-mcu/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/openhwgroup","download_url":"https://codeload.github.com/openhwgroup/core-v-mcu/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcore-v-mcu/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28655029,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-22T01:17:37.254Z","status":"online","status_checked_at":"2026-01-22T02:00:07.137Z","response_time":144,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["microcontroller","openhwgroup","riscv","systemverilog"],"created_at":"2024-11-06T05:15:33.692Z","updated_at":"2026-01-22T05:02:42.119Z","avatar_url":"https://github.com/openhwgroup.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0)\n[![Documentation Status](https://readthedocs.org/projects/core-v-mcu/badge/?version=latest)](https://core-v-mcu.readthedocs.io/en/latest/?badge=latest)\n\n# CORE-V MCU\n\nCORE-V MCU originated from PULPissimo \\[[1](https://ieeexplore.ieee.org/abstract/document/8640145)\\], \\[[2](https://ieeexplore.ieee.org/document/9369856)\\],\nand is now a stand-alone project within OpenHW Group independent from PULPIssimo.\n\nIn case you would be interested to join the project please feel free to open an issue, or involve yourself in any open issues/discussions.\nContributions are always welcome!\nFirst time contributors should review the [Contributing](https://github.com/openhwgroup/core-v-mcu/tree/master/CONTRIBUTING.md) guide.\n\n## Quick Start Guide\n\nThe fastest way to get up and running with the CORE-V MCU is with pre-built bit streams for the Digilent Nexys A7 board.\nCheck out the [Quick Start Guide](https://github.com/openhwgroup/core-v-mcu/tree/master/emulation/quickstart/README.md).\n\n## Getting Started\n\nInstall the required Python tools:\n\n```\npip3 install --user -r python-requirements.txt\n```\n\nInstall fusesoc: https://fusesoc.readthedocs.io/en/stable/user/installation.html#ug-installation\n\nInstall Verilator v4.100: https://verilator.org/guide/latest/install.html\n\nInstall Xilinx Vivado: see the [Quick Start Guide](https://github.com/openhwgroup/core-v-mcu/tree/master/emulation/quickstart/README.md).\n\n## Building\n\nThe build system uses make to capture the required steps.\nmake with no argments will print a list of the current targets:\n```\n$ make\nall:            generate build scripts, custom build files, doc and sw header files\nbitstream:      generate nexysA7-100T.bit file for emulation\nmodel-lib:      build a Verilator model library\nlint:           run Verilator lint check\ndocs:           generate documentation\nsw:             generate C header files (in ./sw)\nnexys-emul:     generate bitstream for Nexys-A7-100T emulation)\ngenesys-emul:   generate bitstream for Genesys2 FPGA board\nbuildsim:       build for Questa sim\nsim:            run Questa sim\ndownloadn:      Download bitstream to Nexys board\ndownloadg:      Download bitstream to Genesys2 board\n```\n\n## Building an FPGA Image\n\nTo target the Nexys-A7-100T board:\n```\n$ make nexys-emul\n```\n\nMake sure you have the latest Xilinx board-parts installed.\nCurrent image is [core_v_nexys_200122.bit](http://core-v-mcu.s3-website-eu-west-1.amazonaws.com/core_v_mcu_nexys_200122.bit)\n\n\nTo target Genesys2 board:\n```\n$ make genesys-emul\n```\nExtra note for building on ubuntu - Vivado tools from Xilinx may require a larger swap size that the system default.\nThe swap size can be increased by searching for \"increase swapfile in ubuntu\" and add your release.\n\n## Building documentation\n\n```\n$ make docs\n```\nThe resulting documents are accessed using file ./docs/\\_build/html/index.html\n\n### Documentation of the Debug Unit\n\nAt present the details of the debug unit are not incorporated in the main\ndocumentation.  The top level interface is an IEEE 1149.1 compliant JTAG Test\nAccess port.  It implements the reference JTAG Debug Transport Module\ndocumented in Section 6.1 of the [RISC-V Debug Interface, version\n0.13.2](https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf).\n\nThe RISC-V Debug Interface has many optional features.  Those enabled for the\nCORE-V MCU are documented in the [PULP Platform Debug\nUnit](https://github.com/pulp-platform/riscv-dbg).\n\n## Building C header files\n\n```\n$ make sw\n```\nThe resulting header files are located in ./sw\n\n## Running Modelsim/Questasim\n\n```\n$ make buildsim sim\n```\nThe 'make buildsim' creates a work library in build/openhwgroup.org_systems_core-v-mcu_0/sim-modelsim, and then 'make sim' runs the simulation.\n\nThe test bench used by the simulation is 'core_v_mcu_tb.sv'\n\nThe resulting header files are located in ./sw\n\n## Experimental fuseSoC Support\n\nRun Verilator lint target:\n\n```\nfusesoc --cores-root . run --target=lint --setup --build openhwgroup.org:systems:core-v-mcu\n```\n\nTo build Verilator as a library which can be linked into other tools (such as\nthe debug server):\n\n```\nfusesoc --cores-root . run --target=model-lib --setup --build openhwgroup.org:systems:core-v-mcu\n```\n\nThe library will be in the `obj_dir` subdirectory of the work root.\n\nOnce can sanity check the top-level using QuestaSim:\n\n```\nfusesoc --cores-root . run --target=sim --setup --build --run openhwgroup.org:systems:core-v-mcu\n```\n\n## Contributing: Pre-commit checks\n\nIf you are submitting a pull-request, it will be subject to pre-commit checks.\nThe two that most likely cause problems are the Verilator Lint check and the Verible format check.\n\n### Verilator model library\n\nThe system will run\n```\nfusesoc --cores-root . run --target=model-lib --setup --build openhwgroup.org:systems:core-v-mcu\n```\nIf your changes introduce any Verilator errors, you either need to fix these, or, if appropriate, add a rule to ignore them to `rtl/core-v-mcu/verilator.waiver`.\n\nThis will create the Verilator library `Vcore_v_mcu_wrapper__ALL.a` in `build/openhwgroup.org_systems_core-v-mcu_0/model-lib-verilator/obj_dir`.\n\nNote that when you use this library to build an application you will need to\nensure that the directory `build/openhwgroup.org_systems_core-v-mcu_0/model-lib-verilator/mem_init` is either symbolically linked or copied to the directory where the application will run. The model will load ROM images from this directory.\n\n**Note.** The model is compiled at optimization level `-O3`, since performance is of importance with the likely applications, and with `-fPIC`, so it is suitable for inclusion in shared object libraries.\n\n### Verilator lint check\n\nThe system will run\n```\nfusesoc --cores-root . run --target=lint --setup --build openhwgroup.org:systems:core-v-mcu\n```\nIf your changes introduce any more Verilator lint warnings, you either need to fix these, or, if appropriate, add a rule to ignore them to `rtl/core-v-mcu/verilator.waiver`.\n\n### Verible format check\n\nStandard formating is enforced by [Verible](https://github.com/chipsalliance/verible).  The command used is\n```\nutil/format-verible\n```\nat the top level of the repository, which will correct the format of any file. The check will fail if any file is changed.\n\nTwo important things to note.\n\n1.  If you do not have Verible installed (which is likely), then `util/format-verible` will silently do nothing.\n\n2.  You must install the correct version of Verible, currently v0.0-3410-g398a8505.  Chips Alliance has [prebuilt versions](https://github.com/chipsalliance/verible/releases?ref=circuitcove.com). The version may change in the future.  In the event of the check failing, the details with the failure will tell you which version was used.\n\n## References\n\n1. [Schiavone, Pasquale Davide, et al. \"Quentin: an ultra-low-power pulpissimo soc in 22nm fdx.\" 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2018.](https://ieeexplore.ieee.org/abstract/document/8640145)\n\n2. [Schiavone, Pasquale Davide, et al. \"Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes.\" IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29.4 (2021): 677-690.](https://ieeexplore.ieee.org/document/9369856)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcore-v-mcu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fopenhwgroup%2Fcore-v-mcu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcore-v-mcu/lists"}