{"id":13537315,"url":"https://github.com/openhwgroup/core-v-verif","last_synced_at":"2025-05-15T03:05:14.532Z","repository":{"id":37033398,"uuid":"224885491","full_name":"openhwgroup/core-v-verif","owner":"openhwgroup","description":"Functional verification project for the CORE-V family of RISC-V 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cores","Assembly","CPUs"],"sub_categories":[],"readme":"\u003c!--\n\n Copyright 2020, 2021 OpenHW Group\n\n Licensed under the Solderpad Hardware Licence, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n     https://solderpad.org/licenses/\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License.\n\n SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0\n\n--\u003e\n\n# core-v-verif\nFunctional verification project for the CORE-V family of RISC-V cores.\n\n\u003c!--\n## NEWS UPDATES:\n**2021-07-15**: The verificaton environment for the [cv32e40s](https://github.com/openhwgroup/cv32e40s) is up and running.\n\u003cbr\u003e\n**2021-03-23**: The verificaton environment for the [cv32e40x](https://github.com/openhwgroup/cv32e40x) is up and running.\n\u003cbr\u003e\n**2020-12-16**: The [cv32e40p_v1.0.0](https://github.com/openhwgroup/core-v-verif/releases/tag/22dc5fc) of core-v-verif is released.\nThis tag clones the v1.0.0 release of the CV32E40P CORE-V core and will allow you to reproduce the verification environment as it existed at `RTL Freeze`.\n\u003cbr\u003e\nMore news is available in the [archive](https://github.com/openhwgroup/core-v-verif/blob/master/NEWS_ARCHIVE.md).\n--\u003e\n\n## Getting Started\nFirst, have a look at the [OpenHW Group's website](https://www.openhwgroup.org) to learn a bit more about who we are and what we are doing.\n\u003cbr\u003e\nFor first time users of CORE-V-VERIF, the **Quick Start Guide** in the [CORE-V-VERIF Verification Strategy](https://docs.openhwgroup.org/projects/core-v-verif/en/latest/quick_start.html) is the best place to start.\n\n\u003c!--\n### Getting started with CV32E4\\* cores\nIf you want to run a simulation there are two options:\n1. To run the CORE testbench for the CV32E40P, go to `cv32e40p/sim/core` and read the README.\n2. To run any of the CV32E4\\* UVM environment go to `mk/uvmt` and read the README.\n--\u003e\n\n\u003c!--\n#### CV32E40P coverage data\nThe most recently published coverage report for the CV32E40P can be found [here](https://openhwgroup.github.io/core-v-verif/).\n--\u003e\n\n\u003c!--\n### Getting started with CVA6\nTo run CVA6 testbench, go to [cva6](cva6) directory and read the README.\n--\u003e\n\n## Directory Structure of this Repo\n### bin\nVarious utilities for running tests and performing various verification-related activities in the core-v-verif repository.\n\n### core-v-cores\nEmpty sub-directory into which the RTL from one or more of the [CORE-V-CORES](https://github.com/openhwgroup/core-v-cores) repositories is cloned.\n\n### cv32e40p, cv32e40x, cv32e40s, cva6\nCore-specific verification code.\n\n### docs\nSources for the Verification Strategy document, DV plans, coding style guidelines and available coverage reports.\n\n### mk\nCommon simulation Makefiles that support testbenches for all CORE-V cores.\n\n### lib\nCommon components for the all CORE-V verification environments.\n\n### vendor_lib\nVerification components supported by third-parties.\n\n## Contributing\nWe highly appreciate community contributions. You can get a sense of our current needs by reviewing the GitHub\n[projects](https://github.com/openhwgroup/core-v-verif/projects) associated with this repository.   Individual work-items\nwithin a project are defined as [issues](https://github.com/openhwgroup/core-v-verif/issues) with a `task` label.\n\u003cbr\u003e\u003cbr\u003eTo ease our work of reviewing your contributions, please:\n\n* Review [CONTRIBUTING](https://github.com/openhwgroup/core-v-verif/blob/master/CONTRIBUTING.md)\nand our [SV/UVM coding style guidelines](https://github.com/openhwgroup/core-v-verif/blob/master/docs/CodingStyleGuidelines.md).\n* Split large contributions into smaller commits addressing individual changes or bug fixes.\nDo not mix unrelated changes into the same commit!\n* Write meaningful commit messages.\n* If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.\n\n## Acknowledgements\n\nCheck out the [acknowledgements](ACKNOWLEDGEMENTS.md).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcore-v-verif","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fopenhwgroup%2Fcore-v-verif","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcore-v-verif/lists"}