{"id":13649110,"url":"https://github.com/openhwgroup/cv-hpdcache","last_synced_at":"2026-02-18T05:36:13.522Z","repository":{"id":101877478,"uuid":"604651903","full_name":"openhwgroup/cv-hpdcache","owner":"openhwgroup","description":"RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV 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High-Performance, Multi-requester, Out-of-Order L1 Dcache for RISC-V cores and accelerators.\n\n\n## Directory Structure\n\n\u003ctable\u003e\n  \u003ctr\u003e\n    \u003cth style=\"text-align:left;width:20%\"\u003eDirectory\u003c/th\u003e\n    \u003cth style=\"text-align:left\"\u003eDescription\u003c/th\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003ertl\u003c/td\u003e\n    \u003ctd\u003eContains the file lists to be used for the compiling of the HPDcache\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003ertl/src\u003c/td\u003e\n    \u003ctd\u003eContains the SystemVerilog RTL sources of the HPDcache\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003ertl/syn\u003c/td\u003e\n    \u003ctd\u003eContains a synthesis flow based on Yosys\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003ertl/lint\u003c/td\u003e\n    \u003ctd\u003eContains a linter wrapper and a Makefile to run a lint tool on the RTL\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003ertl/tb\u003c/td\u003e\n    \u003ctd\u003eContains a HPDcache standalone testbench for validation of the RTL\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003ertl/fv/lnt\u003c/td\u003e\n    \u003ctd\u003eContains a formal HPDcache specification written in LNT\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003edocs\u003c/td\u003e\n    \u003ctd\u003eContains documentation of the HPDcache\u003c/td\u003e\n  \u003c/tr\u003e\n\u003c/table\u003e\n\n\n## Documentation\n\nThe HPDcache User Guide document can be found in the *docs* folder.\nIt is written in reStructuredText format.\n\nIf you need to compile the User Guide document, a dedicated *Makefile* is in the *docs* folder.\n\nYou can find some pre-compiled User Guide documents (in both HTML or PDF) in [Releases](https://github.com/openhwgroup/cv-hpdcache/releases)\n\n\n## Licensing\n\nThe HPDcache is released under the Solderpad Hardware License (version 2.1).\nPlease refer to the [LICENSE](LICENSE) file for further information.\n\n\n## Integration Examples of the HPDcache\n\n### CVA6\n\nThe HPDcache is integrated with the CVA6 core.\nThe HPDcache repository (this repository) is included as a submodule of the CVA6 Git.\nAfter you clone the [CVA6](https://github.com/openhwgroup/cva6) repository, be sure to pass the ``config_pkg::HPDCACHE`` value to the ``DCacheType`` parameter.\nThis selects the HPDcache as the L1 Data Cache of the core.\nFor example, the CVA6 configuration package [cv64a6_imafdc_sv39_hpdcache_config_pkg.sv](https://github.com/openhwgroup/cva6/blob/master/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv) does this.\n\nThe HPDcache is instantiated in the [cva6_hpdcache_subsystem.sv](https://github.com/openhwgroup/cva6/blob/master/core/cache_subsystem/cva6_hpdcache_subsystem.sv) file.\nYou may take a look if you want to integrate the HPDcache with another core.\n\n### Integration Template\n\nYou may look into the docs/lint subdirectory of this repository to see an integration example of the HPDcache ([hpdcache_lint.sv](docs/lint/hpdcache_lint.sv)).\n\nThis example uses the macros defined in the [hpdcache_typedef.svh](rtl/include/hpdcache_typedef.svh) file.\nThese macros ease the definition of types required by the interface of the HPDcache module.\n\n## HPDcache Validation and Verification\n\nFor a complete UVM testbench of the HPDcache, please see the [HPDcache Verif](https://github.com/openhwgroup/cv-hpdcache-verif) repository.\n\nThere is another testbench (not as complete as the one above) written in SystemC into the `rtl/tb` subdirectory of this repository.\nThis testbench is compatible with the [Verilator](https://www.veripool.org/verilator/) simulation tool. Thus, it accepts a fully open-source simulation flow.\nFor more information about the SystemC testbench, read its dedicated [README](rtl/tb/README.md).\n\n\n## HPDcache Publications \u0026 Tutorials\n\n- Technical Paper: César Fuguet. 2023. HPDcache: Open-Source High-Performance L1 Data Cache for RISC-V Cores. In Proceedings of the 20th ACM International Conference on Computing Frontiers (CF '23). Association for Computing Machinery, New York, NY, USA, 377–378. \u003chttps://doi.org/10.1145/3587135.3591413\u003e\n\n- Technical Paper: D. Million, N. Oliete-Escuín and C. Fuguet, \"Breaking the Memory Wall with a Flexible Open-Source L1 Data-Cache,\" 2024 Design, Automation \u0026 Test in Europe Conference \u0026 Exhibition (DATE), Valencia, Spain, 2024, pp. 1-2, \u003chttps://doi.org/10.23919/DATE58400.2024.10546547\u003e\n\n- Video: César Fuguet. 2023. High Performance L1 Dcache for RISC-V Cores. TRISTAN Workshop. RISC-V Summit Europe 2023. \u003chttps://www.youtube.com/watch?v=3r5STMiUq9s\u003e\n\n- Video: Christian Fabre, César Fuguet. 2023. One Year of Improvements on OpenHW Group's HPDCache. RISC-V Summit US 2023. \u003chttps://www.youtube.com/watch?v=ODHA-wPOmW0\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcv-hpdcache","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fopenhwgroup%2Fcv-hpdcache","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcv-hpdcache/lists"}