{"id":13427702,"url":"https://github.com/openhwgroup/cv32e40p","last_synced_at":"2026-02-16T09:37:40.904Z","repository":{"id":37081678,"uuid":"52028445","full_name":"openhwgroup/cv32e40p","owner":"openhwgroup","description":"CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform","archived":false,"fork":false,"pushed_at":"2025-02-12T18:01:56.000Z","size":11425,"stargazers_count":1043,"open_issues_count":60,"forks_count":445,"subscribers_count":82,"default_branch":"master","last_synced_at":"2025-04-13T21:17:55.741Z","etag":null,"topics":["riscv","riscv32imfc"],"latest_commit_sha":null,"homepage":"https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/openhwgroup.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":"CITATION.cff","codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2016-02-18T18:21:33.000Z","updated_at":"2025-04-13T19:53:49.000Z","dependencies_parsed_at":"2023-11-07T10:25:15.919Z","dependency_job_id":"dbf3676c-5895-4638-aff9-74f830807326","html_url":"https://github.com/openhwgroup/cv32e40p","commit_stats":null,"previous_names":["pulp-platform/riscv"],"tags_count":60,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcv32e40p","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcv32e40p/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcv32e40p/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcv32e40p/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/openhwgroup","download_url":"https://codeload.github.com/openhwgroup/cv32e40p/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248782259,"owners_count":21160717,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["riscv","riscv32imfc"],"created_at":"2024-07-31T01:00:38.695Z","updated_at":"2025-10-15T13:53:25.280Z","avatar_url":"https://github.com/openhwgroup.png","language":"SystemVerilog","funding_links":[],"categories":["CPU cores","SystemVerilog","Uncategorized","Open Source Implementations","CPU RISC-V","Open Source implementations","Open Source Core Implementations"],"sub_categories":["Uncategorized","Cores","网络服务_其他"],"readme":"[![Build Status](https://travis-ci.com/pulp-platform/riscv.svg?branch=master)](https://travis-ci.com/pulp-platform/riscv)\n\n# OpenHW Group CORE-V CV32E40P RISC-V IP\n\nCV32E40P is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements\nthe RV32IM\\[F|Zfinx\\]C instruction set architecture, and the PULP custom extensions for achieving\nhigher code density, performance, and energy efficiency \\[[1](https://doi.org/10.1109/TVLSI.2017.2654506)\\], \\[[2](https://doi.org/10.1109/PATMOS.2017.8106976)\\].\nIt started its life as a fork of the OR10N CPU core that is based on the OpenRISC ISA.\nThen, under the name of RI5CY, it became a RISC-V core (2016), and it has been maintained\nby the [PULP platform](https://www.pulp-platform.org/) team until February 2020,\nwhen it has been contributed to [OpenHW Group](https://www.openhwgroup.org/).\n\n\u003cp align=\"center\"\u003e\u003cimg src=\"docs/images/CV32E40P_Block_Diagram.svg\" width=\"750\"\u003e\u003c/p\u003e\n\n## Documentation\n\nThe CV32E40P user manual can be found in the _docs_ folder and it is\ncaptured in reStructuredText, rendered to html using [Sphinx](https://docs.readthedocs.io/en/stable/intro/getting-started-with-sphinx.html).\nThese documents are viewable using readthedocs and can be viewed [here](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/).\n\n## Verification\nThe verification environment for the CV32E40P is _not_ in this Repository.  There is a small, simple testbench here which is\nuseful for experimentation only and should not be used to validate any changes to the RTL prior to pushing to the master\nbranch of this repo.\n\nThe verification environment for this core as well as other cores in the OpenHW Group CORE-V family is at the\n[core-v-verif](https://github.com/openhwgroup/core-v-verif) repository on GitHub.\n\nThe Makefiles supported in the **core-v-verif** project automatically clone the appropriate version of the **cv32e40p**  RTL sources.\n\n## Changelog\n\nA changelog is generated automatically in the documentation from the individual pull requests.\nIn order to enable automatic changelog generation within the CV32E40P documentation, the committer is required to label each pull request\nthat touches any file in 'rtl' (or any of its subdirectories) with *Component:RTL* and label each pull request that touches any file in\n'docs' (or any of its subdirectories) with *Component:Doc*. Pull requests that are not labeled or labeled with *ignore-for-release* are\nignored for the changelog generation.\n\nOnly the person who actually performs the merge can add these labels (you need committer rights). The changelog flow only works if at most\n1 label is applied and therefore pull requests that touches both RTL and documentation files in the same pull request are not allowed.\n\n## Constraints\nExample synthesis constraints for the CV32E40P are provided.\n\n## Contributing\n\nWe highly appreciate community contributions. We are currently using the lowRISC contribution guide.\nTo ease our work of reviewing your contributions,\nplease:\n\n* Create your own fork to commit your changes and then open a Pull Request to the **dev** branch.\n* Split large contributions into smaller commits addressing individual changes or bug fixes. Do not\n  mix unrelated changes into the same commit!\n* Do not mix updates within the 'rtl' directory with updates within the 'docs' directory ino the same pull request.\n* Write meaningful commit messages. For more information, please check out the [the Ibex contribution\n  guide](https://github.com/lowrisc/ibex/blob/master/CONTRIBUTING.md).\n* If asked to modify your changes, do fixup your commits and rebase your branch to maintain a\n  clean history.\n* If the PR gets accepted and merged into the the **dev** branch, an action is triggered automatically to check whether the changes are logically equivalent to the frozen RTL on a given set of parameters. If the changes are logically equivalent, the **dev** branch is automatically merged into the **master** branch. Otherwise, we need to investigate manually. If a bug is found, thus the changes are not logically equivalent, we follow the procedure documented [here](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/core_versions.html). \n\nFor more details on how this is implemented, have a look at this [page](https://github.com/openhwgroup/cv32e40p/blob/master/.github/workflows/aws_cv32e40p.md).\n\nWhen contributing SystemVerilog source code, please try to be consistent and adhere to [the lowRISC Verilog\ncoding style guide](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md).\n\nTo get started, please check out the [\"Good First Issue\"\n list](https://github.com/openhwgroup/cv32e40p/issues?q=is%3Aissue+is%3Aopen+-label%3Astatus%3Aresolved+label%3A%22good+first+issue%22).\n\nThe RTL code has been formatted with [\"Verible\"](https://github.com/google/verible) v0.0-1149-g7eae750.\nRun `./util/format-verible` to format all the files.\n\n## Issues and Troubleshooting\n\nIf you find any problems or issues with CV32E40P or the documentation, please check out the [issue\n tracker](https://github.com/openhwgroup/cv32e40p/issues) and create a new issue if your problem is\nnot yet tracked.\n\n## References\n\n1. [Gautschi, Michael, et al. \"Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices.\"\n in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 10, pp. 2700-2713, Oct. 2017](https://doi.org/10.1109/TVLSI.2017.2654506)\n\n2. [Schiavone, Pasquale Davide, et al. \"Slow and steady wins the race? A comparison of\n ultra-low-power RISC-V cores for Internet-of-Things applications.\"\n _27th International Symposium on Power and Timing Modeling, Optimization and Simulation\n (PATMOS 2017)_](https://doi.org/10.1109/PATMOS.2017.8106976)\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcv32e40p","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fopenhwgroup%2Fcv32e40p","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcv32e40p/lists"}