{"id":13649111,"url":"https://github.com/openhwgroup/cv32e40x","last_synced_at":"2026-01-26T13:03:02.469Z","repository":{"id":37097239,"uuid":"341497701","full_name":"openhwgroup/cv32e40x","owner":"openhwgroup","description":"4 stage, in-order, compute RISC-V core based on the CV32E40P","archived":false,"fork":false,"pushed_at":"2024-11-06T11:19:59.000Z","size":9834,"stargazers_count":226,"open_issues_count":36,"forks_count":53,"subscribers_count":17,"default_branch":"master","last_synced_at":"2025-04-13T21:17:55.074Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"https://docs.openhwgroup.org/projects/cv32e40x-user-manual/en/latest/","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/openhwgroup.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-02-23T09:23:27.000Z","updated_at":"2025-04-07T09:46:26.000Z","dependencies_parsed_at":"2023-10-16T19:41:13.389Z","dependency_job_id":"b908bfcf-7a46-4495-bc3e-020d69d4a430","html_url":"https://github.com/openhwgroup/cv32e40x","commit_stats":null,"previous_names":[],"tags_count":10,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcv32e40x","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcv32e40x/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcv32e40x/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcv32e40x/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/openhwgroup","download_url":"https://codeload.github.com/openhwgroup/cv32e40x/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248782259,"owners_count":21160717,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:47.220Z","updated_at":"2026-01-26T13:02:57.447Z","avatar_url":"https://github.com/openhwgroup.png","language":"SystemVerilog","funding_links":[],"categories":["SystemVerilog","CPUs"],"sub_categories":[],"readme":"# OpenHW Group CORE-V CV32E40X RISC-V IP\n\nCV32E40X is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements the following instruction set architecture:\n\n* RV32[I|E]\n* [A]\n* [M|Zmmul]\n* Zca_Zcb_Zcmp_Zcmt\n* [Zba_Zbb_Zbs|Zba_Zbb_Zbc_Zbs]\n* Zicntr\n* Zihpm\n* Zicsr\n* Zifencei\n* [Xif]\n\nThe CV32E40X core is aimed\nat compute intensive applications and offers a general purpose extension interface by which custom instructions\ncan be added external to the core.\n\nIt started its life as a fork of the OpenHW CV32E40P core that in its turn was based on the RI5CY core from\nthe [PULP platform](https://www.pulp-platform.org/) team.\n\n## Documentation\n\nThe CV32E40X user manual can be found in the _docs_ folder and it is\ncaptured in reStructuredText, rendered to html using [Sphinx](https://docs.readthedocs.io/en/stable/intro/getting-started-with-sphinx.html).\nThese documents are viewable using readthedocs and can be viewed [here](https://docs.openhwgroup.org/projects/cv32e40x-user-manual/en/latest/).\n\n## Verification\nThe verification environment for the CV32E40X is _not_ in this Repository.\n\nThe verification environment for this core as well as other cores in the OpenHW Group CORE-V family is at the\n[core-v-verif](https://github.com/openhwgroup/core-v-verif) repository on GitHub.\n\nThe Makefiles supported in the **core-v-verif** project automatically clone the appropriate version of the **CV32E40X**  RTL sources.\n\n## Constraints\nExample synthesis constraints for the CV32E40X are provided.\n\n## Contributing\nWe highly appreciate community contributions.\n\u003cbr\u003e\u003cbr\u003eTo ease our work of reviewing your contributions, please:\n\n* Review [CONTRIBUTING](https://github.com/openhwgroup/cv32e40x/blob/master/CONTRIBUTING.md).\n* Create your own fork to commit your changes and then open a Pull Request.\n* Split large contributions into smaller commits addressing individual changes or bug fixes. Do not\n  mix unrelated changes into the same commit!\n* If asked to modify your changes, do fixup your commits and rebase your branch to maintain a\n  clean history.\n\nWhen contributing SystemVerilog source code, please try to be consistent and adhere to [the lowRISC Verilog\ncoding style guide](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md).\n\nTo get started, please check out the [\"Good First Issue\"\n list](https://github.com/openhwgroup/cv32e40x/issues?q=is%3Aissue+is%3Aopen+-label%3Astatus%3Aresolved+label%3A%22good+first+issue%22).\n\n## Commit Messages\nPlease take the time to write meaningful commit messages.\nThe following are adopted from [lowRISC Ibex](https://github.com/lowrisc/ibex/blob/master/CONTRIBUTING.md):\n\n- Create your branch to commit your changes and then create a Pull Request.\n- Separate subject from body with a blank line.\n- Limit the subject line to 50 characters.\n- Capitalize the subject line.\n- Do not end the subject line with a period.\n- Use the imperative mood in the subject line.\n- Use the present tense (\"Add feature\" not \"Added feature\").\n- Wrap the body at 72 characters.\n- Use the body to explain what and why vs. how.\n\nFor a detailed why and how please refer to one of the multiple [resources](https://chris.beams.io/posts/git-commit/) regarding git commit messages.\n\nIf you use `vi` for your commit message, consider to put the following snippet inside your `~/.vimrc`:\n\n```\nautocmd Filetype gitcommit setlocal spell textwidth=72\n```\n\n## Issues and Troubleshooting\nIf you find any problems or issues with CV32E40X or the documentation, please check out the [issue\n tracker](https://github.com/openhwgroup/cv32e40x/issues) and create a new issue if your problem is\nnot yet tracked.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcv32e40x","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fopenhwgroup%2Fcv32e40x","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcv32e40x/lists"}