{"id":13408565,"url":"https://github.com/openhwgroup/cva6","last_synced_at":"2025-05-13T22:03:57.699Z","repository":{"id":37787934,"uuid":"118652371","full_name":"openhwgroup/cva6","owner":"openhwgroup","description":"The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux","archived":false,"fork":false,"pushed_at":"2025-04-23T20:26:50.000Z","size":145952,"stargazers_count":2443,"open_issues_count":205,"forks_count":750,"subscribers_count":92,"default_branch":"master","last_synced_at":"2025-04-23T21:31:44.220Z","etag":null,"topics":["ariane","asic","cpu","fpga","risc-v","rv64gc","systemverilog-hdl"],"latest_commit_sha":null,"homepage":"https://docs.openhwgroup.org/projects/cva6-user-manual/","language":"Assembly","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/openhwgroup.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":"CITATION.cff","codeowners":"CODEOWNERS","security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2018-01-23T18:36:12.000Z","updated_at":"2025-04-23T20:26:55.000Z","dependencies_parsed_at":"2023-09-27T18:14:12.594Z","dependency_job_id":"9c1aaeba-a2d4-467f-9cde-4c6b27c08b79","html_url":"https://github.com/openhwgroup/cva6","commit_stats":{"total_commits":5689,"total_committers":190,"mean_commits":"29.942105263157895","dds":0.8690455264545615,"last_synced_commit":"86a80f0eaa4ddbe79360a817f3fd332c6a8e3c09"},"previous_names":[],"tags_count":12,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcva6","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcva6/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcva6/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcva6/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/openhwgroup","download_url":"https://codeload.github.com/openhwgroup/cva6/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":251338809,"owners_count":21573613,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["ariane","asic","cpu","fpga","risc-v","rv64gc","systemverilog-hdl"],"created_at":"2024-07-30T20:00:53.698Z","updated_at":"2025-04-28T15:32:30.068Z","avatar_url":"https://github.com/openhwgroup.png","language":"Assembly","readme":"# CVA6 RISC-V CPU [![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml) [![CVA6 dashboard](https://riscv-ci.pages.thales-invia.fr/dashboard/badge_master.svg)](https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_cva6.html) [![Documentation Status](https://readthedocs.com/projects/openhw-group-cva6-user-manual/badge/?version=latest)](https://docs.openhwgroup.org/projects/cva6-user-manual/?badge=latest) [![GitHub release](https://img.shields.io/github/release/openhwgroup/cva6?include_prereleases=\u0026sort=semver\u0026color=blue)](https://github.com/openhwgroup/cva6/releases/)\n\nCVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13.\n\nIt has a configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.\n\nA performance model of CVA6 is available in the `perf-model/` folder of this repository.\nIt can be used to investigate performance-related micro-architecture changes.\n\n\u003cimg src=\"docs/03_cva6_design/_static/ariane_overview.drawio.png\"/\u003e\n\n\n# Quick setup\n\nThe following instructions will allow you to compile and run a Verilator model of the CVA6 APU (which instantiates the CVA6 core) within the CVA6 APU testbench (corev_apu/tb).\n\nThroughout all build and simulations scripts executions, you can use the environment variable `NUM_JOBS` to set the number of concurrent jobs launched by `make`:\n- if left undefined, `NUM_JOBS` will default to 1, resulting in a sequential execution\nof `make` jobs;\n- when setting `NUM_JOBS` to an explicit value, it is recommended not to exceed 2/3 of\nthe total number of virtual cores available on your system.    \n\n1. Checkout the repository and initialize all submodules.\n```sh\ngit clone https://github.com/openhwgroup/cva6.git\ncd cva6\ngit submodule update --init --recursive\n```\n\n2. Install the GCC Toolchain [build prerequisites](util/toolchain-builder/README.md#Prerequisites) then [the toolchain itself](util/toolchain-builder/README.md#Getting-started).\n\n:warning: It is **strongly recommended** to use the toolchain built with the provided scripts.\n\n3. Install `cmake`, version 3.14 or higher.\n\n4. Set the RISCV environment variable.\n```sh\nexport RISCV=/path/to/toolchain/installation/directory\n```\n\n5. Install `help2man` and `device-tree-compiler` packages.\n\nFor Debian-based Linux distributions, run :\n\n```sh\nsudo apt-get install help2man device-tree-compiler\n```\n\n6. Install the riscv-dv requirements:\n\n```sh\npip3 install -r verif/sim/dv/requirements.txt\n```\n\n7. Run these commands to install a custom Spike and Verilator (i.e. these versions must be used to simulate the CVA6) and [these](#running-regression-tests-simulations) tests suites.\n```sh\n# DV_SIMULATORS is detailed in the next section\nexport DV_SIMULATORS=veri-testharness,spike\nbash verif/regress/smoke-tests.sh\n```\n\n# Running standalone simulations\n\nSimulating the CVA6 is done by using `verif/sim/cva6.py`.\n\nThe environment variable `DV_SIMULATORS` allows you to specify which simulator to use.\n\nFour simulation types are supported:\n- **veri-testharness**: verilator with corev_apu/testharness testbench\n- **vcs-testharness**: vcs with corev_apu/testharness testbench\n- **vcs-uvm**: vcs with UVM testbench\n- **Spike** ISS \n\nYou can set several simulators, such as :\n\n```sh\nexport DV_SIMULATORS=veri-testharness,vcs-testharness,vcs_uvm\n```\n\nIf exactly 2 simulators are given, their trace is compared ([see the Regression tests section](#running-regression-tests-simulations)).\n\nHere is how you can run the hello world C program with the Verilator model: \n\n```sh\n# Make sure to source this script from the root directory \n# to correctly set the environment variables related to the tools\nsource verif/sim/setup-env.sh\n\n# Set the NUM_JOBS variable to increase the number of parallel make jobs\n# export NUM_JOBS=\n\nexport DV_SIMULATORS=veri-testharness\n\ncd ./verif/sim\n\npython3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml \\\n--c_tests ../tests/custom/hello_world/hello_world.c \\\n--linker=../../config/gen_from_riscv_config/linker/link.ld \\\n--gcc_opts=\"-static -mcmodel=medany -fvisibility=hidden -nostdlib \\\n-nostartfiles -g ../tests/custom/common/syscalls.c \\\n../tests/custom/common/crt.S -lgcc \\\n-I../tests/custom/env -I../tests/custom/common\"\n```\n\nYou can run either assembly programs (check `verif/test/custom/hello_world/custom_test_template.S`) or C programs. Run `python3 cva6.py --help` to have more informations on the available parameters.\n\n## Simulating with VCS and Verdi\n\nYou can set the environment variable `VERDI` as such if you want to launch Verdi while simulating with VCS:\n\n```sh\nexport VERDI=1\n```\n\n\n# Running regression tests simulations\n\nThe smoke-tests script installs a random instruction generator and several tests suites:\n- [riscv-dv](https://github.com/chipsalliance/riscv-dv)\n- [riscv-compliance](https://github.com/lowRISC/riscv-compliance)\n- [riscv-tests](https://github.com/riscv-software-src/riscv-tests)\n- [riscv-arch-test](https://github.com/riscv-non-isa/riscv-arch-test)\n\n\nThe regression tests are done by comparing a model simulation trace with the Spike trace.\n\nSeveral tests scripts can be found in `./verif/regress`\n\nFor example, here is how would run the riscv-arch-test regression test suite with the Verilator model:\n\n```sh\nexport DV_SIMULATORS=veri-testharness,spike\nbash verif/regress/dv-riscv-arch-test.sh\n```\n\n\n# Logs\n\nThe logs from cva6.py are located in `./verif/sim/out_YEAR-MONTH-DAY`.\n\nAssuming you ran the smoke-tests scripts in the previous step, here is the log directory hierarchy:\n\n- **directed_asm_tests/**: The compiled (to .o then .bin) assembly tests\n- **directed_c_tests/**: The compiled (to .o then .bin) c tests\n- **spike_sim/**: Spike simulation log and trace files\n- **veri_testharness_sim**: Verilator simulation log and trace files\n- **iss_regr.log**: The regression test log \n\nThe regression test log summarizes the comparison between the simulator trace and the Spike trace. Beware that a if a test fails before the comparison step, it will not appear in this log, check the output of cva6.py and the logs of the simulation instead.\n\n\n# Waveform generation\n\nWaveform generation is currently supported for Verilator (`veri-testharness`)\nand VCS with full UVM testbench (`vcs-uvm`) simulation types.  It is disabled\nby default to save simulation time and storage space.\n\nTo enable waveform generation for a supported simulation mode, set either\nof the two shell variables that control tracing before running any of the\ntest scripts under `verif/regress`:\n- `export TRACE_FAST=1` enables \"fast\" waveform generation (keep simulation\n   time low at the expense of space).  This will produce VCD files when using\n   Verilator, and VPD files when using Synopsys VCS with UVM testbench (`vcs-uvm`).\n- `export TRACE_COMPACT=1` enables \"compact\" waveform generation (keep waveform\n   files smaller at the expense of increased simulation time).  This will\n   produce FST files when using Verilator, and FSDB files when using Synopsys\n   VCS with UVM testbench (`vcs-uvm`).\n\nTo generate VCD waveforms of the `smoke-tests` regression suite using Verilator, use:\n```sh\nexport DV_SIMULATORS=veri-testharness,spike\nexport TRACE_FAST=1\nbash verif/regress/smoke-tests-\u003ccpu_version\u003e.sh\n```\n\nWhere `\u003ccpu_version\u003e` is one of the following, depending on the CPU variant you want to use.\n- `cv32a65x`.\n- `cv32a6_imac_sv32`.\n- `cv64a6_imafdc_sv39`.\n\nAfter each simulation run involving Verilator or VCS, the generated waveforms\nwill be copied  to the directory containing the log files (see above,) with\nthe name of the current HW configuration added to the file name right before\nthe file type suffix (e.g., `I-ADD-01.cv32a60x.vcd`).\n\n\n# Physical Implementation\n\n## ASIC Synthesis\n\nHow to make cva6 synthesis ?\n```\nmake -C pd/synth cva6_synth FOUNDRY_PATH=/your/techno/basepath/ TECH_NAME=yourTechnoName TARGET_LIBRARY_FILES=\"yourLib1.db\\ yourLib2.db\" PERIOD=10 NAND2_AREA=650 TARGET=cv64a6_imafdc_sv39 ADDITIONAL_SEARCH_PATH=\"others/libs/paths/one\\ others/libs/paths/two\"\n```\nDon't forget to escape spaces in lists.\nReports are under: pd/synth/ariane/reports\n\n\n## ASIC Gate Simulation with `core-v-verif` repository\n\n\u003e :warning: **Warning**: this chapter needs to be updated. See Github issue https://github.com/openhwgroup/cva6/issues/1358.\n\n```sh\nexport DV_SIMULATORS=veri-testharness,spike\ncva6/regress/smoke-tests.sh\nmake -C pd/synth cva6_synth FOUNDRY_PATH=/your/techno/basepath/ TECH_NAME=yourTechnoName TARGET_LIBRARY_FILES=\"yourLib1.db\\ yourLib2.db\" PERIOD=10 NAND2_AREA=650 TARGET=cv64a6_imafdc_sv39 ADDITIONAL_SEARCH_PATH=\"others/libs/paths/one\\ others/libs/paths/two\"\nsed 's/module SyncSpRamBeNx64_1/module SyncSpRamBeNx64_2/' pd/synth/ariane_synth.v \u003e pd/synth/ariane_synth_modified.v\ncd cva6/sim\nmake vcs_clean\npython3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-ld --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=spike,vcs-core-gate $DV_OPTS\n```\n\n\n# COREV-APU FPGA Emulation\n\nWe currently provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual) and the [Agilex 7 Development Kit](https://www.intel.la/content/www/xl/es/products/details/fpga/development-kits/agilex/agf014.html).\n\n- **Genesys 2**\n    \n    We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/openhwgroup/cva6/releases).\n\n    Tested on Vivado 2018.2. The FPGA currently contains the following peripherals:\n\n   - DDR3 memory controller\n   - SPI controller to conncet to an SDCard\n   - Ethernet controller\n   - JTAG port (see debugging section below)\n   - Bootrom containing zero stage bootloader and device tree.\n   - UART\n   - GPIOs connected to LEDs\n\n\u003e The ethernet controller and the corresponding network connection is still work in progress and not functional at the moment. Expect some updates soon-ish.\n\n- **Agilex 7**\n  \n   Tested on Quartus Prime Version 24.1.0 Pro Edition. The FPGA currently contains the following peripherals:\n  \n   - DDR4 memory controller\n   - JTAG port (see debugging section below)\n   - Bootrom containing zero stage bootloader\n   - UART\n   - GPIOs connected to LEDs\n\n\u003e The ethernet controller and the corresponding network connection, as well as the SD Card connection and the capability to boot linux are still work in progress and not functional at the moment. Expect some updates soon-ish. \n\n\n## Programming the Memory Configuration File or bitstream\n\n- **Genesys 2**\n\n   - Open Vivado\n   - Open the hardware manager and open the target board (Genesys II - `xc7k325t`)\n   - Tools - Add Configuration Memory Device\n   - Select the following Spansion SPI flash `s25fl256xxxxxx0`\n   - Add `ariane_xilinx.mcs`\n   - Press Ok. Flashing will take a couple of minutes.\n   - Right click on the FPGA device - Boot from Configuration Memory Device (or press the program button on the FPGA)\n\n- **Agilex 7**\n\n   - Open Quartus programmer\n   - Configure HW Setup by selecting the AGF FPGA Development Kit\n   - Click Auto-Detect to scan the JTAG chain\n   - In the device list, right click over device AGFB014R24B and add file (.sof)\n   - Click on Start button to program the FPGA\n   - Right now only baremetal is supported, so right after programming you can connect to the UART and see your CVA6 alive on Agilex!\n   - For this you need to use the JTAG UART provided with Quartus installation\n\n```\n.$quartus_installation_path/qprogrammer/quartus/bin/juart-terminal \njuart-terminal: connected to hardware target using JTAG UART on cable\njuart-terminal: \"AGF FPGA Development Kit [1-3]\", device 1, instance 0\njuart-terminal: (Use the IDE stop button or Ctrl-C to terminate)\n\nHello World!\n```\n\n## Preparing the SD Card\n\nThe first stage bootloader will boot from SD Card by default. Get yourself a suitable SD Card (we use [this](https://www.amazon.com/Kingston-Digital-Mobility-MBLY10G2-32GB/dp/B00519BEQO) one). Either grab a pre-built Linux image from [here](https://github.com/pulp-platform/ariane-sdk/releases) or generate the Linux image yourself following the README in the [ariane-sdk repository](https://github.com/pulp-platform/ariane-sdk). Prepare the SD Card by following the \"Booting from SD card\" section in the ariane-sdk repository.\n\nConnect a terminal to the USB serial device opened by the FTDI chip e.g.:\n```\nscreen /dev/ttyUSB0 115200\n```\n\nDefault baudrate set by the bootlaoder and Linux is `115200`.\n\nAfter you've inserted the SD Card and programmed the FPGA you can connect to the serial port of the FPGA and should see the bootloader and afterwards Linux booting. Default username is `root`, no password required.\n\n\n## Generating a Bitstream\n\n- **Genesys 2**\n\nTo generate the FPGA bitstream (and memory configuration) yourself for the Genesys II board run:\n\n```\nmake fpga\n```\n\nThis will produce a bitstream file and memory configuration file (in `fpga/work-fpga`) which you can permanently flash by running the above commands.\n\n- **Agilex 7**\n\nTo generate the FPGA bitstream yourself for the Agilex 7 board run:\n\n```\nmake altera\n```\n\nWe recommend to set the parameter FpgaAlteraEn (and also FpgaEn) to benefit from the FPGA optimizations.\n\nThis will produce a bitstream file (in `altera/output_files`) which you can program following the previous instructions. **Note: Bear in mind that you need a Quartus Pro Licence to be able to generate this bitstream**\n\nTo clean the project after generating the bitstream, use \n\n```\nmake clean-altera\n```\n\n## Debugging\n\n- **Genesys 2**\nYou can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD below.\n\nTo get started, connect the micro USB port that is labeled with JTAG to your machine. This port is attached to the FTDI 2232 USB-to-serial chip on the Genesys 2 board, and is usually used to access the native JTAG interface of the Kintex-7 FPGA (e.g. to program the device using Vivado). However, the FTDI chip also exposes a second serial link that is routed to GPIO pins on the FPGA, and we leverage this to wire up the JTAG from the RISC-V debug module.\n\n\u003eIf you are on an Ubuntu based system you need to add the following udev rule to `/etc/udev/rules.d/99-ftdi.rules`\n\u003e```\n\u003e SUBSYSTEM==\"usb\", ACTION==\"add\", ATTRS{idProduct}==\"6010\", ATTRS{idVendor}==\"0403\", MODE=\"664\", GROUP=\"plugdev\"\n\u003e```\n\nOnce attached to your system, the FTDI chip should be listed when you type `lsusb`:\n\n```\nBus 005 Device 019: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC\n```\n\nIf this is the case, you can go on and start openocd with the `fpga/ariane.cfg` configuration file:\n\n```\nopenocd -f fpga/ariane.cfg\n\nOpen On-Chip Debugger 0.10.0+dev-00195-g933cb87 (2018-09-14-19:32)\nLicensed under GNU GPL v2\nFor bug reports, read\n    http://openocd.org/doc/doxygen/bugs.html\nadapter speed: 1000 kHz\nInfo : auto-selecting first available session transport \"jtag\". To override use 'transport select \u003ctransport\u003e'.\nInfo : clock speed 1000 kHz\nInfo : TAP riscv.cpu does not have IDCODE\nInfo : datacount=2 progbufsize=8\nInfo : Examined RISC-V core; found 1 harts\nInfo :  hart 0: XLEN=64, misa=0x8000000000141105\nInfo : Listening on port 3333 for gdb connections\nReady for Remote Connections\nInfo : Listening on port 6666 for tcl connections\nInfo : Listening on port 4444 for telnet connections\nInfo : accepting 'gdb' connection on tcp/3333\n```\n- **Agilex 7**\n\nYou can debug (and program) the FPGA using a modified version of OpenOCD included with Quartus installation ($quartus_installation_path/qprogrammer/quartus/bin/openocd). \n\nTo get started, connect the micro USB port that is labeled with J13 to your machine. It is the same port that is used for the UART. Both use the JTAG interface and connect to the System Level Debugging (SLD) Hub instantiated inside the FPGA. Then the debugger connection goes to the virtual JTAG IP (vJTAG) which can be accessed with the modified version of OpenOCD.\n\nYou can start openocd with the `altera/cva6.cfg` configuration file:\n\n```\n./$quartus_installation_path/qprogrammer/quartus/bin/openocd -f altera/cva6.cfg \nOpen On-Chip Debugger 0.11.0-R22.4\nLicensed under GNU GPL v2\nFor bug reports, read\n        http://openocd.org/doc/doxygen/bugs.html\nInfo : only one transport option; autoselect 'jtag'\nInfo : Application name is OpenOCD.20241016093010\nInfo : No cable specified, so will be searching for cables\n\nInfo : At present, The first hardware cable will be used [1 cable(s) detected]\nInfo : Cable 1: device_name=(null), hw_name=AGF FPGA Development Kit, server=(null), port=1-3, chain_id=0x559319c8cde0, persistent_id=1, chain_type=1, features=34816, server_version_info=Version 24.1.0 Build 115 03/21/2024 SC Pro Edition\nInfo : TAP position 0 (C341A0DD) has 3 SLD nodes\nInfo :     node  0 idcode=00406E00 position_n=0\nInfo :     node  1 idcode=30006E00 position_n=0\nInfo :     node  2 idcode=0C006E00 position_n=0\nInfo : TAP position 1 (20D10DD) has 1 SLD nodes\nInfo :     node  0 idcode=0C206E00 position_n=0\nInfo : Discovered 2 TAP devices\nInfo : Detected device (tap_position=0) device_id=c341a0dd, instruction_length=10, features=12, device_name=AGFB014R24A(.|R1|R2)/..\nInfo : Found an Intel device at tap_position 0.Currently assuming it is SLD Hub\nInfo : Detected device (tap_position=1) device_id=020d10dd, instruction_length=10, features=4, device_name=VTAP10\nInfo : Found an Intel device at tap_position 1.Currently assuming it is SLD Hub\nInfo : This adapter doesn't support configurable speed\nInfo : JTAG tap: agilex7.fpga.tap tap/device found: 0xc341a0dd (mfg: 0x06e (Altera), part: 0x341a, ver: 0xc)\nInfo : JTAG tap: auto0.tap tap/device found: 0x020d10dd (mfg: 0x06e (Altera), part: 0x20d1, ver: 0x0)\nInfo : JTAG tap: agilex7.fpga.tap Parent Tap found: 0xc341a0dd (mfg: 0x06e (Altera), part: 0x341a, ver: 0xc)\nInfo : Virtual Tap/SLD node 0x00406E00 found at tap position 0 vtap position 0\nWarn : AUTO auto0.tap - use \"jtag newtap auto0 tap -irlen 10 -expected-id 0x020d10dd\"\nInfo : datacount=2 progbufsize=8\nInfo : Examined RISC-V core; found 1 harts\nInfo :  hart 0: XLEN=32, misa=0x40141107\nInfo : starting gdb server for agilex7.cva6.0 on 3333\nInfo : Listening on port 3333 for gdb connections\nReady for Remote Connections\nInfo : Listening on port 6666 for tcl connections\nInfo : Listening on port 4444 for telnet connections\n```\n\n- **Common for both boards**\n\nThen you will be able to either connect through `telnet` or with `gdb`:\n\n```\nrisc-none-elf-gdb /path/to/elf\n\n(gdb) target remote localhost:3333\n(gdb) load\nLoading section .text, size 0x6508 lma 0x80000000\nLoading section .rodata, size 0x900 lma 0x80006508\n(gdb) b putchar\n(gdb) c\nContinuing.\n\nProgram received signal SIGTRAP, Trace/breakpoint trap.\n0x0000000080009126 in putchar (s=72) at lib/qprintf.c:69\n69    uart_sendchar(s);\n(gdb) si\n0x000000008000912a  69    uart_sendchar(s);\n(gdb) p/x $mepc\n$1 = 0xfffffffffffdb5ee\n```\n\nYou can read or write device memory by using:\n```\n(gdb) x/i 0x1000\n    0x1000: lui t0,0x4\n(gdb) set {int} 0x1000 = 22\n(gdb) set $pc = 0x1000\n```\n\n\n## Preliminary Support for OpenPiton Cache System\n\nCVA6 has preliminary support for the OpenPiton distributed cache system from Princeton University. To this end, a different L1 cache subsystem (`src/cache_subsystem/wt_cache_subsystem.sv`) has been developed that follows a write-through protocol and that has support for cache invalidations and atomics.\n\nThe corresponding integration patches will be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton). Check the `README` in that repository to see how to use CVA6 in the OpenPiton setting.\n\nTo activate the different cache system, compile your code with the macro `DCACHE_TYPE`.\n\n\n## Re-generating the Bootcode (ZSBL)\n\nThe zero stage bootloader (ZSBL) for RTL simulation lives in `bootrom/` while the bootcode for the FPGA is in `fpga/src/bootrom`. The RTL bootcode simply jumps to the base of the DRAM where the FSBL takes over. For the FPGA the ZSBL performs additional housekeeping. Both bootloader pass the hartid as well as address to the device tree in argumen register `a0` and `a1` respectively.\n\nTo re-generate the bootcode you can use the existing makefile within those directories. To generate the SystemVerilog files you will need the `bitstring` python package installed on your system.\n\n\n# Directory Structure:\n\nThe directory structure separates the [CVA6 RISC-V CPU](#cva6-risc-v-cpu) core from the [CORE-V-APU FPGA Emulation Platform](#corev-apu-fpga-emulation).\nFiles, directories and submodules under `cva6` are for the core _only_ and should not have any dependencies on the APU.\nFiles, directories and submodules under `corev_apu` are for the FPGA Emulation platform.\nThe CVA6 core can be compiled stand-alone, and obviously the APU is dependent on the core.\n\nThe top-level directories of this repo:\n* **ci**: Scriptware for CI.\n* **common**: Source code used by both the CVA6 Core and the COREV APU. Subdirectories from here are `local` for common files that are hosted in this repo and `submodules` that are hosted in other repos.\n* **core**: Source code for the CVA6 Core only. There should be no sources in this directory used to build anything other than the CVA6 core.\n* **corev_apu**: Source code for the CVA6 APU, exclusive of the CVA6 core. There should be no sources in this directory used to build the CVA6 core.\n* **docs**: Documentation.\n* **pd**: Example and CI scripts to synthesis CVA6.\n* **util**: General utility scriptware.\n* **vendor**: Third-party IP maintained outside the repository.\n* **verif**: Verification environment for the CVA6. The verification files shared with other cores are in the [core-v-verif](https://github.com/openhwgroup/core-v-verif) repository on GitHub. core-v-verif is defined as a cva6 submodule.\n\n\n## verif Directories\n\n- **bsp**:     board support package for test-programs compiled/assembled/linked for the CVA6.\nThis BSP is used by both `core` testbench and `uvmt_cva6` UVM verification environment.\n- **regress**: scripts to install tools, test suites, CVA6 code and to execute tests\n- **sim**:     simulation environment (e.g. riscv-dv)\n- **tb**:      testbench module instancing the core\n- **tests**:   source of test cases and test lists\n\n# Planned Improvements\n\nGo to the CVA6 Kanban Board which also loosely tracks planned improvements.\n\n\n# Contributing\n\nWe highly appreciate community contributions.\n\u003cbr\u003e\u003cbr\u003eTo ease the work of reviewing contributions, please review [CONTRIBUTING](CONTRIBUTING.md).\n\n\n# Issues and Troubleshooting\n\nIf you find any problems or issues with CVA6 or the documentation, please check out the [issue tracker](https://github.com/openhwgroup/cva6/issues)\nand create a new issue if your problem is not yet tracked.\n\n\n# Publication\n\nIf you use CVA6 in your academic work you can cite us:\n\n\u003cdetails\u003e\n\u003csummary\u003eCVA6 Publication\u003c/summary\u003e\n\u003cp\u003e\n```\n@article{zaruba2019cost,\n   author={F. {Zaruba} and L. {Benini}},\n   journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},\n   title={The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology},\n   year={2019},\n   volume={27},\n   number={11},\n   pages={2629-2640},\n   doi={10.1109/TVLSI.2019.2926114},\n   ISSN={1557-9999},\n   month={Nov},\n}\n```\n\u003c/p\u003e\n\u003c/details\u003e\n\u003cbr/\u003e\n\n\n# Resources and Ecosystem\n\nThe CVA6 core is part of a vivid ecosystem. In [this document](RESOURCES.md), we gather pointers to this ecosystem (building blocks, designs, partners...)\n\n# Acknowledgements\n\nCheck out the [acknowledgements](ACKNOWLEDGEMENTS.md).\n","funding_links":[],"categories":["Projects and IPs","CPU cores","Assembly","Uncategorized","SystemVerilog","CPUs","CPU RISC-V","Open Source implementations","Open Source Core Implementations"],"sub_categories":["Information Technology","Uncategorized","网络服务_其他"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcva6","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fopenhwgroup%2Fcva6","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcva6/lists"}