{"id":13775517,"url":"https://github.com/openhwgroup/cve2","last_synced_at":"2025-05-11T07:32:52.220Z","repository":{"id":40392852,"uuid":"225635855","full_name":"openhwgroup/cve2","owner":"openhwgroup","description":"The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.","archived":false,"fork":true,"pushed_at":"2025-04-08T19:29:25.000Z","size":11309,"stargazers_count":38,"open_issues_count":168,"forks_count":30,"subscribers_count":6,"default_branch":"main","last_synced_at":"2025-04-08T20:30:50.463Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":"lowRISC/ibex","license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/openhwgroup.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2019-12-03T14:10:17.000Z","updated_at":"2025-03-21T00:51:46.000Z","dependencies_parsed_at":null,"dependency_job_id":"bc69e62e-e2e2-4de4-bc8e-70d913cfcbc3","html_url":"https://github.com/openhwgroup/cve2","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcve2","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcve2/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcve2/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/openhwgroup%2Fcve2/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/openhwgroup","download_url":"https://codeload.github.com/openhwgroup/cve2/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253534084,"owners_count":21923515,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-03T17:01:40.120Z","updated_at":"2025-05-11T07:32:47.210Z","avatar_url":"https://github.com/openhwgroup.png","language":"SystemVerilog","funding_links":[],"categories":["CPUs"],"sub_categories":[],"readme":"# OpenHW Group CORE-V CVE2 RISC-V IP\n\nCVE2 is a class of 2-stage pipeline OpenHW Group cores. Currently, the only core in this class is the CV32E20.\nCV32E20 is a fork of the [Ibex](https://github.com/lowRISC/ibex) core.\nDifferently to Ibex, cv32e2 will target low cost as originally intended in the [Zero-riscy](https://doi.org/10.1109/PATMOS.2017.8106976) project.\nThe core will be made compatible with the OpenHW Group OBI protocol, it will use the same sleep unit of CV32E4 family, and it will achieve TRL5 with the industrial-level verification [core-v-verif](https://github.com/openhwgroup/core-v-verif).\n\n# CV32E20 RISC-V Core\n\nCV32E20 is a production-quality open source source 32-bit RISC-V CPU core written in\nSystemVerilog. The CPU core is heavily parametrizable and well-suited for\nembedded control applications. CV32E20 is being extensively verified and has\nseen multiple tape-outs. CV32E20 supports the Integer (I) or Embedded (E),\nInteger Multiplication and Division (M), and Compressed (C) extensions.\n\nThe block diagram below shows the *small* parametrization with a 2-stage\npipeline.\n\n\u003cp align=\"center\"\u003e\u003cimg src=\"doc/03_reference/images/blockdiagram.svg\" width=\"650\"\u003e\u003c/p\u003e\n\nCV32E20 was initially developed as part of the [PULP platform](https://www.pulp-platform.org)\nunder the name [\u0026#34;Zero-riscy\u0026#34;](https://doi.org/10.1109/PATMOS.2017.8106976), and has been\ncontributed to [lowRISC](https://www.lowrisc.org) who maintains it and develops it further.\nIt was further adopted by the OpenHW Group to work towards an improved industrialization\n\n## Verification\n\nThe verification environment for the CVE2 is _not_ in this Repository.  There is a small, simple testbench here which is\nuseful for experimentation only and should not be used to validate any changes to the RTL prior to pushing to the master\nbranch of this repo.\n\nThe verification environment for this core as well as other cores in the OpenHW Group CORE-V family is at the\n[core-v-verif](https://github.com/openhwgroup/core-v-verif) repository on GitHub.\n\nThe Makefiles supported in the **core-v-verif** project automatically clone the appropriate version of the **cve2** RTL sources.\n\n## Changelog\n\nA changelog is generated automatically in the documentation from the individual pull requests.\nIn order to enable automatic changelog generation within the documentation, the committer is required to label each pull request\nthat touches any file in 'rtl' (or any of its subdirectories) with *Component:RTL* and label each pull request that touches any file in\n'docs' (or any of its subdirectories) with *Component:Doc*. Pull requests taht are not labeled or labeled with *ignore-for-release* are\nignored for the changelog generation.\n\nOnly the person who actually performs the merge can add these labels (you need committer rights). The changelog flow only works if at most\n1 label is applied and therefore pull requests that touch both RTL and documentation files in the same pull request are not allowed.\n\n## Configuration\n\nCV32E20 offers several configuration parameters to meet the needs of various application scenarios.\nThe options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features.\nThe table below indicates performance, area, and verification status for a few selected configurations.\nThese are configurations on which lowRISC is focusing for performance evaluation and design verification (see [supported configs](cve2_configs.yaml)).\n\n| Config                            | \"micro\" | \"small\"               |\n| --------------------------------- | ------- | --------------------- |\n| Features                          | RV32EC  | RV32IMC, 3 cycle mult |\n| Performance (CoreMark/MHz)        | 0.904   | 2.47                  |\n| Area - Yosys (kGE)                | 16.85   | 26.60                 |\n| Area - Commercial (estimated kGE) | ~15     | ~24                   |\n| Verification status               |         |                       |\n\nNotes:\n\n* Performance numbers are based on CoreMark running on the CV32E20 Simple System [platform](examples/simple_system/README.md).\n  Note that different ISAs (use of B and C extensions) give the best results for different configurations.\n  See the [Benchmarks README](examples/sw/benchmarks/README.md) for more information.\n* Yosys synthesis area numbers are based on the CV32E20 basic synthesis [flow](syn/README.md) using the latch-based register file.\n* Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.\n* For comparison, the original \"zero-riscy\" core yields an area of 23.14kGE using our Yosys synthesis flow.\n* Verification status is a rough guide to the overall maturity of a particular configuration.\n  Green indicates that verification is close to complete.\n  Amber indicates that some verification has been performed, but the configuration is still experimental.\n  Red indicates a configuration with minimal/no verification.\n* v.1.0.0 of the RISC-V Bit-Manipulation Extension is supported as well as the remaining sub-extensions of draft v.0.93 of the bitmanip spec.\n  The latter is *not ratified* and there may be changes before ratification.\n  See [Standards Compliance](https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html) in the Ibex documentation for more information.\n\n## Documentation (to be updated)\n\nThe CVE2 documentation can be\n[read online at ReadTheDocs](https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/). It is also contained in\nthe `doc` folder of this repository.\n\n## Examples\n\nThe CVE2 repository includes [Simple System](examples/simple_system/README.md).\nThis is an intentionally simple integration of CV32E20 with a basic system that targets simulation.\nIt is intended to provide an easy way to get bare metal binaries running on CV32E20 in simulation.\n\n## Contributing\n\nWe highly appreciate community contributions. We are currently using the lowRISC contribution guide.\nTo ease our work of reviewing your contributions,\nplease:\n\n* Create your own fork to commit your changes and then open a Pull Request to the **dev** branch.\n* Split large contributions into smaller commits addressing individual changes or bug fixes. Do not\n  mix unrelated changes into the same commit!\n* Do not mix updates within the 'rtl' directory with updates within the 'docs' directory into the same pull request.\n* Write meaningful commit messages. For more information, please check out the [the Ibex contribution\n  guide](https://github.com/lowrisc/ibex/blob/master/CONTRIBUTING.md).\n* If asked to modify your changes, do fix up your commits and rebase your branch to maintain a\n  clean history.\n* If the PR gets accepted and merged into the **dev** branch, an action is triggered automatically to check whether the changes are logically equivalent to the frozen RTL on a given set of parameters. If the changes are logically equivalent, the **dev** branch is automatically merged into the **master** branch. Otherwise, we need to investigate manually. If a bug is found, thus the changes are not logically equivalent, we follow the procedure documented [here](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/core_versions.html).\n\nFor more details on how this is implemented, have a look at this [page](https://github.com/openhwgroup/cv32e40p/blob/master/.github/workflows/aws_cv32e40p.md).\n\nWhen contributing SystemVerilog source code, please try to be consistent and adhere to [the lowRISC Verilog\ncoding style guide](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md).\n\nTo get started, please check out the [\u0026#34;Good First Issue\u0026#34;\n list](https://github.com/openhwgroup/cv32e40p/issues?q=is%3Aissue+is%3Aopen+-label%3Astatus%3Aresolved+label%3A%22good+first+issue%22).\n\nThe RTL code has been formatted with [\u0026#34;Verible\u0026#34;](https://github.com/google/verible) v0.0-1149-g7eae750.\nRun `./util/format-verible` to format all the files.\n\n## Issues and Troubleshooting\n\nIf you find any problems or issues with CVE2 or the documentation, please check out the [issue\n tracker](https://github.com/openhwgroup/cve2/issues) and create a new issue if your problem is\nnot yet tracked.\n\n## License\n\nUnless otherwise noted, everything in this repository is covered by the Apache\nLicense, Version 2.0 (see LICENSE for full text).\n\n## Credits\n\nMany people have contributed to CVE2 and its predecessor projects through the years. Please have a look at\nthe [credits file](CREDITS.md) and the commit history for more information.\n\n## References\n\n[Schiavone, Pasquale Davide, et al. \"Slow and steady wins the race? A comparison of\n ultra-low-power RISC-V cores for Internet-of-Things applications.\"\n _27th International Symposium on Power and Timing Modeling, Optimization and Simulation\n (PATMOS 2017)_](https://doi.org/10.1109/PATMOS.2017.8106976)\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcve2","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fopenhwgroup%2Fcve2","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fopenhwgroup%2Fcve2/lists"}