{"id":13440708,"url":"https://github.com/oreboot/oreboot","last_synced_at":"2025-05-14T04:07:29.836Z","repository":{"id":37734110,"uuid":"173800499","full_name":"oreboot/oreboot","owner":"oreboot","description":"oreboot is a fork of coreboot, with C removed, written in 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oreboot README\n\n[![Build Status](https://github.com/oreboot/oreboot/actions/workflows/build.yml/badge.svg)](https://github.com/oreboot/oreboot/actions/workflows/build.yml)\n\n![oreboot logo](Documentation/img/logo-small.png)\n\noreboot is a downstream fork of coreboot, i.e. oreboot is coreboot without 'c'.\n\noreboot is mostly written in Rust, with assembly where needed.\n\noreboot currently only plans to support LinuxBoot payloads.\n\n## Demos\n\n- [oreboot for ARM in QEMU](https://asciinema.org/a/Ne4Fwa4Wpt95dorEoVnHwiEkP)\n- [oreboot for RISC-V HiFive Unleashed in QEMU](https://asciinema.org/a/XnWkMWTABuajsbGPMMTefjuZ2)\n\n\u003cdetails\u003e\n  \u003csummary\u003eOutput sample from oreboot on Allwinner D1\u003c/summary\u003e\n\n```\noreboot 🦀\nv 13\ncpu_pll fa001000\ncpu_axi 5000100\ncpu_axi 5000100\nperi0_ctrl was: f8216300\nperi0_ctrl lock en\nperi0_ctrl PLLs\nperi0_ctrl set: f8216300\nDDR3@792MHz\ntest OK\n512M 🐏\nNOR flash: c2/2018\nload 00018000 bytes to 40000000: ➡️.\nload 00fc0000 bytes to 44000000: ➡️➡️➡️➡️➡️➡️➡️➡️➡️➡️➡️➡️➡️➡️➡️➡️.\nload 00010000 bytes to 41a00000: ➡️.\n{ɕ serial uart0 initialized\nRISC-V vendor 5b7 arch 0 imp 0\n==== platform CSRs ====\n   MXSTATUS  c0408000\n   MHCR      00000109\n   MCOR      00000002\n   MHINT     00004000\nsee C906 manual p581 ff\n=======================\nSet up extension CSRs\n==== platform CSRs ====\n   MXSTATUS  c0638000\n   MHCR      0000017f\n   MCOR      00000003\n   MHINT     0000610c\nsee C906 manual p581 ff\n=======================\ntimer init\nreset init\nipi init\nRustSBI version 0.3.1\n.______       __    __      _______.___________.  _______..______   __\n|   _  \\     |  |  |  |    /       |           | /       ||   _  \\ |  |\n|  |_)  |    |  |  |  |   |   (----`---|  |----`|   (----`|  |_)  ||  |\n|      /     |  |  |  |    \\   \\       |  |      \\   \\    |   _  \u003c |  |\n|  |\\  \\----.|  `--'  |.----)   |      |  |  .----)   |   |  |_)  ||  |\n| _| `._____| \\______/ |_______/       |__|  |_______/    |______/ |__|\nPlatform Name: T-HEAD Xuantie Platform\nImplementation: oreboot version 0.1.0\n[rustsbi] misa: RV64ACDFIMSUVX\n[rustsbi] mideleg: ssoftstimersext (0x222)\n[rustsbi] medeleg: imaialmalasmasauecallipagelpagespage(0xb1f3)\n[rustsbi] mie: msoft ssoft mtimer stimer mext sext (00000aaa)\nPMP0     0x0 - 0x40000000 (A,R,W,X)\nPMP1     0x40000000 - 0x40200000 (A,R)\nPMP2     0x40200000 - 0x80000000 (A,R,W,X)\nPMP3     0x80000000 - 0x80200000 (A,R)\nPMP4     0x80200000 - 0xfffff800 (A,R,W,X)\nPMP8     0x0 - 0x0 (A,R,W,X)\nDTB looks fine, yay!\nDecompress 12375521 bytes from 0x44000004 to 0x40200000, reserved 25165824 bytes\nSuccess, decompressed 21910144 bytes :)\nPayload looks like Linux Image, yay!\nDTB still fine, yay!\nHanding over to SBI, will continue at 0x40200000\nenter supervisor at 40200000 with DTB from 41a00000\n...\n[    0.000000] OF: fdt: Ignoring memory range 0x40000000 - 0x40200000\n[    0.000000] Machine model: Sipeed Lichee RV Dock\n[    0.000000] earlycon: sbi0 at I/O port 0x0 (options '')\n[    0.000000] printk: bootconsole [sbi0] enabled\n[    0.000000] Zone ranges:\n[    0.000000]   DMA32    [mem 0x0000000040200000-0x000000005fffffff]\n[    0.000000]   Normal   empty\n[    0.000000] Movable zone start for each node\n[    0.000000] Early memory node ranges\n[    0.000000]   node   0: [mem 0x0000000040200000-0x000000005fffffff]\n[    0.000000] Initmem setup node 0 [mem 0x0000000040200000-0x000000005fffffff]\n[    0.000000] riscv: SBI specification v1.0 detected\n[    0.000000] riscv: SBI implementation ID=0x4 Version=0x301\n[    0.000000] riscv: SBI TIME extension detected\n[    0.000000] riscv: SBI IPI extension detected\n[    0.000000] riscv: SBI SRST extension detected\n[    0.000000] riscv: base ISA extensions acdfim\n[    0.000000] riscv: ELF capabilities acdfim\n[    0.000000] percpu: Embedded 17 pages/cpu s31912 r8192 d29528 u69632\n[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 128520\n[    0.000000] Kernel command line: console=tty0 console=ttyS0,115200 loglevel=7 earlycon=sbi\n```\n\n\u003c/details\u003e\n\n## Rust Embedded\n\n![Rust Embedded Working Group Logo](Documentation/img/rust-embedded-logo.png)\n\nWe build on top of the abstractions from the [Rust Embedded Working Group](https://github.com/rust-embedded)'s model with its crates and traits, detailed\nin [their book](https://docs.rust-embedded.org/book/portability/index.html).\n\nIn a nutshell: ![Rust Embedded Model](Documentation/img/rust-embedded-model.png)\n\n## Vendor support\n\nSoC vendors are expected to provide documentation to their cores, peripherals\nand other blocks and/or their SVD files, so that we can generate the PAC and HAL\ncrates, or ideally, the vendor should _provide and maintain_ those as well.\n\nThe Rust Embedded book offers [design patterns and implementation guidelines](https://docs.rust-embedded.org/book/design-patterns/hal/index.html) as well as\na [glossary](https://docs.rust-embedded.org/book/appendix/glossary.html) to gain\nan understanding of the structure.\n\n## Boot Flow and Setup\n\nTo get a general understanding of how oreboot and firmware in general works,\nhave a look at the [boot flow documentation](Documentation/boot-flow.md). It\ndescribes how firmware is stored and boots up on a platform / SoC.\n\n## Dilemma of drivers\n\nNote that oreboot does not aim to turn into its own operating system.\nAccordingly, we intend to keep the amount and functionality of drivers low.\nHowever, by design of SoCs, we do have to implement something to load code:\n\n- SPI flash, SD cards and eMMC are rather simple to load from, but require\n  special mechanisms and tools to write to the storage part\n- USB and ethernet are more flexible for development as they allow for loading\n  code from another machine, but are more complex to implement\n- UART is simple for data transfer, but very slow for larger payloads, such as\n  a Linux kernel\n\nIn many cases, no full driver is needed, since we only need to e.g. read from\nstorage, and we need no rich file systems. To avoid colliding with the needs and\nspecifics of an OS, we recommend clearly separating storage parts holding the\nfirmware and operating system, respectively. For example, put the firmware in a\nSPI flash and the OS on an NVMe SSD.\n\n## Getting oreboot\n\nClone this repo and enter its directory, i.e.:\n\n```sh\ngit clone https://github.com/oreboot/oreboot.git\ncd oreboot\n```\n\n## Prerequisites\n\nIn general, you will need the following packages installed:\n\n- `device-tree-compiler`\n- `pkg-config`\n- `libssl`\n- `rustup`\n\nFor Debian based systems, there is a make target to install those, which pulls\n`rustup` through curl from https://sh.rustup.rs:\n\n```sh\nmake debiansysprepare\n```\n\nOtherwise, install the package through your system package manager.\n\n## Setting up the toolchain\n\nRegardless of your OS, you will need to install the toolchain for oreboot.\nThis command only needs to be done once but it is safe to do it repeatedly.\n\n```sh\nmake firsttime\n```\n\n## Keeping build tools up to date\n\nEach time you start to work with oreboot, or even daily:\n\n```sh\ncd oreboot\nmake update\n```\n\nYou should definitely do this before reporting any issues.\n\n## Developing oreboot\n\nThere are two different things in the project:\n\n1. `src/mainboards/*` the actual targets; those depend on and share crates, which\n   can be drivers, SoC init code, and similar. For mainboards, `Cargo.lock`\n   **must** be tracked.\n2. `src/*` everything else; these are the aforementioned crates, for which, we\n   do not track the `Cargo.lock` files.\n\nChecking in a mainboard's `Cargo.lock` file records the state of its dependencies\nat the time of a successful build, enabling reproducibility. Ideally, a lock file\nis updated follwoing successful boot on hardware.\n\nFor more, see: https://doc.rust-lang.org/cargo/faq.html#why-do-binaries-have-cargolock-in-version-control-but-not-libraries\n\nWhen creating a new mainboard, looking at how others are set up for the same\narchitecture is a good start. Be aware that oreboot is targeting bare metal, so\nthere is no standard library available.\n\n## Building oreboot\n\nTo build oreboot for a specific platform, do this:\n\n```\n# Go to the mainboard's directory\ncd src/mainboard/sunxi/nezha\n# Build the mainboard target\nmake mainboard\n# View disassembly\nmake objdump\n# Run from RAM without flashing\nmake run\n# Flash to the board\nmake flash\n```\n\nThe root `Makefile` allows you to quickly build all platforms:\n\n```\n# build all mainboards\nmake mainboards\n# build everything in parallel\nmake -j mainboards\n```\n\n## QEMU\n\n```\n# Install QEMU for your target platform, e.g. x86\nsudo apt install qemu-system-x86\n\n# Build release build and start with QEMU\ncd src/mainboard/emulation/qemu-q35 \u0026\u0026 make run\n# Quit qemu with CTRL-A X\n```\n\nTo build QEMU from source for RISC-V:\n\n```\ngit clone https://github.com/qemu/qemu \u0026\u0026 cd qemu\nmkdir build-riscv64 \u0026\u0026 cd build-riscv64\n../configure --target-list=riscv64-softmmu\nmake -j$(nproc)\n# QEMU binary is at riscv64-softmmu/qemu-system-riscv64\n```\n\nTo build QEMU from source for aarch64:\n\n```\ngit clone https://github.com/qemu/qemu \u0026\u0026 cd qemu\nmkdir build-aarch64 \u0026\u0026 cd build-aarch64\n../configure --target-list=aarch64-softmmu\nmake -j$(nproc)\n# QEMU binary is at aarch64-softmmu/qemu-system-aarch64\n```\n\n## Mainboards\n\nSimilar to coreboot, the structure in oreboot is per vendor and mainboard.\nMultiple architectures and SoCs are supported respectively, and their common\ncode is shared between the boards. Boards may have variants if minor deviations\nwould otherwise cause too much code duplication.\n\n### Emulation\n\n- `qemu-riscv`\n\n### Hardware\n\n#### RISC-V\n\n##### Allwinner D1 SoC\n\n- Sipeed Lichee RV Dock / Dock Pro\n- MangoPi MQ-Pro\n- DongshanPi Nezha STU\n- Allwinner Nezha\n\n### Previous Implementations\n\nFor reference, [earlier approaches are documented](graveyard.md). Have a look at\nthose for x86 and Arm platforms and mainboards.\n\n### Parked for Revival\n\nEarlier emulation targets have been parked in `src.broken/mainboard/emulation/`.\nThey are supposed to provide a general understanding of each architecture that\noreboot seeks to support:\n\n- `qemu-armv7`\n- `qemu-aarch64`\n- `qemu-q35`\n\n## Ground Rules\n\n- `Makefile`s must be simple. Use `xtask` instead for control flow, e.g., adding\n  headers or checksums to the binaries, sitchting images, etc..\n- `Cargo.toml` in the respective `src/mainboard/$VENDOR/$BOARD` (sub)directories\n  allow for board-specific dependencies and building all stages in parallel.\n- All code and markup is auto-formatted with `make format` with no exceptions.\n  A CI check will tell if a change does not adhere to the formatting rules.\n- There will be no code written in C. We write all code in Rust.\n- We will not run our own Gerrit. We are using GitHub for now, and the GitHub\n  Pull Request review mechanism.\n- We will not run our own Jenkins. We will use the most appropriate CI; for\n  now, that is GitHub, but we will be flexible.\n\n## Copyright and License\n\nThe copyright on oreboot is owned by quite a large number of individual\ndevelopers and companies. Please check the individual source files for details.\n\noreboot is licensed under the terms of the GNU General Public License (GPL).\nSome files are licensed under the \"GPL (version 2, or any later version)\",\nand some files are licensed under the \"GPL, version 2\". For some parts, which\nwere derived from other projects, other (GPL-compatible) licenses may apply.\nPlease check the individual source files for details.\n\nThis makes the resulting oreboot images licensed under the GPL, version 2.\n","funding_links":[],"categories":["Development tools","HarmonyOS","Applications","Rust","Uncategorized","Misc","Boot firmware","rust"],"sub_categories":["Embedded","Windows Manager","System tools","Uncategorized","First stage"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Foreboot%2Foreboot","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Foreboot%2Foreboot","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Foreboot%2Foreboot/lists"}