{"id":16334389,"url":"https://github.com/origami404/minirv-chisel","last_synced_at":"2025-04-10T11:35:17.099Z","repository":{"id":190350732,"uuid":"682440572","full_name":"Origami404/MiniRV-Chisel","owner":"Origami404","description":"2023 年学校 CPU 设计课程作业, 一个使用 Chisel 编写的简单 RV32I CPU 核心","archived":false,"fork":false,"pushed_at":"2023-08-24T07:10:07.000Z","size":4569,"stargazers_count":8,"open_issues_count":1,"forks_count":0,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-03-24T20:21:56.245Z","etag":null,"topics":["chisel3","cpu","hitsz","homework"],"latest_commit_sha":null,"homepage":"","language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"agpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Origami404.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2023-08-24T07:09:06.000Z","updated_at":"2024-08-06T04:17:43.000Z","dependencies_parsed_at":"2023-08-24T08:32:41.109Z","dependency_job_id":"d86bedf4-d0b1-4fa7-9785-08ea656641cc","html_url":"https://github.com/Origami404/MiniRV-Chisel","commit_stats":null,"previous_names":["origami404/minirv-chisel"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Origami404%2FMiniRV-Chisel","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Origami404%2FMiniRV-Chisel/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Origami404%2FMiniRV-Chisel/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Origami404%2FMiniRV-Chisel/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Origami404","download_url":"https://codeload.github.com/Origami404/MiniRV-Chisel/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248208689,"owners_count":21065205,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel3","cpu","hitsz","homework"],"created_at":"2024-10-10T23:38:16.604Z","updated_at":"2025-04-10T11:35:12.083Z","avatar_url":"https://github.com/Origami404.png","language":"Scala","funding_links":[],"categories":[],"sub_categories":[],"readme":"# MiniRV-Chisel\n\n\u003e 为了防止实验指导书年年更新, 当年的实验指导书仓库 fork [在此](https://github.com/Origami404/cpu-guide-2023-fork)\n\n本项目为本人的 [2023 年学校 CPU 设计课程](https://hitsz-cslab.gitee.io/cpu/) 的实验, 实现了一个简单的 RV32I CPU, 功能如下:\n\n- 使用 Chisel 开发, 集成了 [学校提供的 verilator 测试框架](https://gitee.com/hitsz-cslab/cdp-tests)\n- 五级流水线: IF, ID, EX, MEM, WB\n- 简单的分支预测 (2-bit) 与前递\n- 支持 rv32i 除 ecall/ebreak 之外的所有指令\n  - sub-word load/store\n- 具有适合于本校 FPGA 板子的 SoC 设备\n  - 本校板子: XC7A100TFGG484-1\n- 通过答辩的形式展示了 Chisel 的优势与本项目的设计\n  - [Slides](pre/新时代%20RTL%20级硬件设计语言.pdf)\n\n它不合理的地方如下:\n\n- 假设内存访存是单周期的\n  - 没有缓存\n- 不支持 ecall/ebreak, 没有任何与特权级相关的功能\n  - 没有 TLB\n- 不支持 CSR 与任何形式的中断与异常\n\n本项目仅作为分享使用, 请勿用于任何正式用途. 请注意学术诚信, 拒绝抄袭.\n\n\u003e ~~不过抄袭的人真会抄我这个吗~~\n\n## 项目结构\n\n```bash\n.\n|-- core        # 核心代码\n|-- macro       # 一些宏定义\n|-- pre         # 答辩 slides\n|-- trace       # 仿真相关文件\n|   |-- asm     # 测试样例汇编\n|   |-- bin     # 测试样例二进制\n|   |-- csrc    # verilator 仿真文件\n|   |-- golden_model\n|   |-- mySoC   # Chisel 生成的 verilog 文件\n|   |-- vsrc    # 仿真用内存模块\n|   |   |-- ram1.v\n|   |   `-- ram.v\n|   |-- Makefile \n|   `-- run_all_tests.py\n|-- build.sbt\n`-- README.md\n```\n\n其中核心文件如下:\n\n```bash\ncore/src/main/scala/top/origami404/miniRV\n|-- io\n|   |-- BlackBox.scala  # 对 Vivado IP 核的包装\n|   |-- Devices.scala   # SoC 上的设备\n|   `-- SoC.scala       # SoC 模块 (上板 Top 模块)\n|-- utils\n|   |-- F.scala         # 一些常用的函数\n|   `-- Main.scala      # Chisel 转换入口\n|-- Components.scala    # CPU 的组件: ALU, 解码器... \n|-- Constants.scala     # 常量定义\n|-- Control.scala       # 不在流水线中的模块: 分支预测, 前递...\n`-- Core.scala          # CPU 核心: 流水线模块与总体模块\n```\n\n## 使用\n\n需要自行安装 `sbt` 与 `verilator`.\n\n### 编译 Chisel\n\n```bash\nsbt \"project root\" \"runMain top.origami404.miniRV.utils.Main\"\n```\n\n编译后会分别生成 `trace/mySoC/CPUCore.v` 和 `vivado/proj_pipeline.srcs/sources_1/new/SoC.v` 两个文件.\n\n### 运行仿真\n\n```bash\ncd trace\nmake TEST=文件名\n```\n\n其中文件名为为 `trace/bin` 下的二进制文件名, 例如 `make TEST=add` 会运行 `trace/bin/add.bin` 这个二进制文件. 也可以使用如下命令运行所有测试:\n\n```bash\nmake build\nmake run_for_python\n```\n\n仿真框架由学校提供, 取自 [cdp-tests](https://gitee.com/hitsz-cslab/cdp-tests), 在此感谢学长的付出.\n\n### 综合与下板\n\n根据 [实验指导书](https://hitsz-cslab.gitee.io/cpu/lab2/2-parts/#1) 进行对应 IP 核的配置与 COE 文件导入. 注意, 本项目使用了四个单 byte 的 BROM 组合成了一个 [多体交叉存储器](https://en.wikipedia.org/wiki/Interleaved_memory), 因此需要将 `start.bin` 二进制文件的每一行 32 bit 的 hex 拆分成四份, 分别导入到四个 BROM 中. \n\n## 感想\n\nChisel 不用一条条接线真的太方便了.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Forigami404%2Fminirv-chisel","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Forigami404%2Fminirv-chisel","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Forigami404%2Fminirv-chisel/lists"}