{"id":46051310,"url":"https://github.com/osvvm/osvvmlibraries","last_synced_at":"2026-03-01T09:01:47.756Z","repository":{"id":37256722,"uuid":"281009137","full_name":"OSVVM/OsvvmLibraries","owner":"OSVVM","description":"Start here.   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from Unit/RTL to full chip/system level testing.\n- Test cases and verification components that can be written any VHDL Engineer.\n- Test cases that are readable and reviewable by the whole team including software and system engineers.   \n- Unmatched reuse through the entire verification process.    \n- Unmatched test reporting with HTML based test suite reports, test case reports, and logs that facilitate debug and test artifact collection.   \n- Support for continuous integration (CI/CD) with JUnit XML test suite reporting.  \n- Powerful and concise verification capabilities including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering that are simple to use and work like built-in language features.\n- A common scripting API to run all simulators - including GHDL, NVC, Aldec Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS, and Cadence Xcelium.  \n- A Co-simulation capability that supports running software (C++) in a hardware simulation environment.\n- A Model Independent Transaction (MIT) library that defines a transaction API (procedures such as read, write, send, get, …)  and transaction interface (a record) that simplifies writing verification components and test cases.\n- A rival to the verification capabilities of SystemVerilog + UVM.  \n\n## Learning OSVVM\nYou can find an overview of OSVVM at [osvvm.github.io](https://osvvm.github.io).\nAlternately you can find our pdf documentation at \n[OSVVM Documentation Repository](https://github.com/OSVVM/Documentation#readme).\n\nYou can also learn OSVVM by taking the class, [Advanced VHDL Verification and Testbenches - OSVVM\u0026trade; BootCamp](https://synthworks.com/vhdl_testbench_verification.htm)\n\n## Run The Demos\nA great way to get oriented with OSVVM is to run the demos.\nFor directions on running the demos, see [OSVVM Scripts](https://github.com/osvvm/OSVVM-Scripts#readme).\n\n## [OsvvmLibraries](https://github.com/osvvm/OsvvmLibraries) \nOsvvmLibraries contains all other OSVVM repositories as submodules.   If you want everything, this is the one you need to clone.   \n\n### Download using git\nBe sure to use “–recursive” to include the submodules:\n```    \n  $ git clone --recursive https://github.com/osvvm/OsvvmLibraries\n```\n\n### Download a Zip file\nGet a zip file from [osvvm.org Downloads Page](https://osvvm.org/downloads).\n\n## [OSVVM Utility Library Repository](https://github.com/osvvm/osvvm#readme) \nThe OSVVM Utility library (named osvvm) implements \nbuzz word verification capabilities including Constrained Random, Functional Coverage, \nScoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering \nthat are simple to use and work like built-in language features.\n\n\n## [OSVVM Verification Script Library Repository](https://github.com/osvvm/OSVVM-Scripts)\nThe OSVVM script library implements\na common scripting API to run all simulators - \nincluding GHDL, NVC, Aldec Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS, and Cadence Xcelium.  \nOur motto: \"One Script to RUn them ALL\"\n  \n## [OSVVM Model Independent Transaction Library Repository](https://github.com/osvvm/OSVVM-Common#readme)\nThe Model Independent Transaction (MIT) library (osvvm_common) defines a transaction API (procedures such as read, write, send, get, …) \nand transaction interface (a record) that simplifies writing verification components and test cases. \nThe MIT library is used (and required) by all OSVVM verification components.\nUsi8ng OSVVM MIT makes verification component deveopment as easy as any \"Lite\" based approach.\n\n\n## The OSVVM Verification Component Libraries\nThe OSVVM Verification Component Libraries are a growing set of \nverification components commonly used for FPGA and ASIC verification.\nEach family of verification components is a separate git repository. \nThe library currently contains the following repositories:\n\n  - [AXI4 Repository](https://github.com/osvvm/AXI4#readme) \n    - Axi4 Full Manager (burst), Memory (burst), Subordinate Verification Components\n    - Axi4 Lite Manager and Subordinate Verification Components\n    - AxiStream Transmitter and Receiver Verification Components\n  - [UART Repository](https://github.com/osvvm/UART#readme) \n    - UART Transmitter and Receiver\n  - [DpRam Repository](https://github.com/osvvm/DpRam) \n    - DpRam behavioral model \n    - DpRam Manager VC to read and write to the DpRam interface\n  - [Ethernet xMII Repository](https://github.com/osvvm/Ethernet) \n    - Verification components for Ethernet Phy and MAC that support GMII/RGMII/MII/RMII.\n\n## [OSVVM Co-simulation Repository](https://github.com/OSVVM/CoSim#readme)\nOSVVM co-simulation supports running software (C++) in a hardware simulation environment.  \nThis includes either writing tests cases in C++ or running C++ models such as instruction set simulators.\n\n## [OSVVM Documentation Repository](https://github.com/OSVVM/Documentation#readme)\nPDF documentation for all things OSVVM.\n\n\n## OSVVM Transaction Interfaces \nOSVVM verification components use records for the \ntransaction interfaces, so connecting them to your \ntestbench is simple - connect only a single signal.\n\nThe OSVVM methodology uses records whose elements\nare a resolved type from the package ResolutionPkg.vhd.  \n\nThe long term plan is to switch to VHDL-2019 interfaces.\nVHDL-2019 uses records just like OSVVM and adds mode \nviews.   So the transition to VHDL-2019 interfaces \nis fairly simple. Due to their similarity, OSVVM \ninterfaces are an effective prototype for VHDL-2019 \ninterfaces.      \n\n## Testbenches are Included \n\nTestbenches are in the Git repository, so you can \nrun a simulation and see a live example \nof how to use the models.\n\n## Participating and Project Organization \nThe OSVVM project welcomes your participation with either \nissue reports or pull requests.\nFor details on [how to participate see](CONTRIBUTING.md)\n\nYou can find the project [Authors here](AUTHORS.md) and\n[Contributors here](CONTRIBUTORS.md).\n\n## More Information on OSVVM\n\n**OSVVM Forums and Blog:**     [http://www.osvvm.org/](http://www.osvvm.org/)   \n**Gitter:** [https://gitter.im/OSVVM/Lobby](https://gitter.im/OSVVM/Lobby)  \n**Documentation:** [osvvm.github.io](https://osvvm.github.io)    \n**Documentation:** [PDF Documentation](https://github.com/OSVVM/Documentation)  \n\n## Copyright and License\nCopyright (C) 2006-2022 by [SynthWorks Design Inc.](http://www.synthworks.com/)  \nCopyright (C) 2022 by [OSVVM Authors](AUTHORS.md)   \n\nThis file is part of OSVVM.\n\n    Licensed under Apache License, Version 2.0 (the \"License\")\n    You may not use this file except in compliance with the License.\n    You may obtain a copy of the License at\n\n  [http://www.apache.org/licenses/LICENSE-2.0](http://www.apache.org/licenses/LICENSE-2.0)\n\n    Unless required by applicable law or agreed to in writing, software\n    distributed under the License is distributed on an \"AS IS\" BASIS,\n    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n    See the License for the specific language governing permissions and\n    limitations under the License.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fosvvm%2Fosvvmlibraries","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fosvvm%2Fosvvmlibraries","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fosvvm%2Fosvvmlibraries/lists"}