{"id":25838354,"url":"https://github.com/ovuiproduction/operating-system-simulator","last_synced_at":"2026-05-13T00:35:45.858Z","repository":{"id":229899309,"uuid":"777952770","full_name":"ovuiproduction/Operating-System-Simulator","owner":"ovuiproduction","description":"The OS Simulator replicates key functionalities like memory management, CPU scheduling, and interrupts. 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Memory Managment\n2. Virtual Memory\n3. Process Execution\n4. Process Scheduling\n5. Interuppt Handling\n\n## Phase - 1\n\n### Problem Statement : \n1. CPU / Machine Simulation\n2. Supervisor Call through interrupt\n\n### Assumption :\n1. Jobs entered without error in input file\n2. No physical separation between jobs\n3. Job outputs separated in output file by 2 blank lines\n4. Program loaded in memory starting at location 00\n5. No multiprogramming, load and run one program at a time\n6. SI interrupts for service request\n\n### NOTATION\n\u003cbr\u003e\nM: memory; \n\u003cbr\u003e\nIR: Instruction Register (4 bytes)\n\u003cbr\u003e\nIR [1, 2]: Bytes 1, 2 of IR/Operation Code\n\u003cbr\u003e\nIR [3, 4]: Bytes 3,4 of IR/Operand Address\n\u003cbr\u003e\nM [\u0026]: Content of memory location\n\u003cbr\u003e\nIC: Instruction Counter Register (2 bytes)\n\u003cbr\u003e\nR: General Purpose Register (4 bytes)\n\u003cbr\u003e\nC: Toggle (1 byte)\n\n\u003chr\u003e\n\n## Phase - 2\n\n### Problem Statement : \n1. CPU / Machine Simulation\n2. Supervisor Call through interrupt\n3. Multiple-Program execution\n4. Error handling in jobs\n5. Handling Program interrupt,Timing interrupt and system interrupt\n\n### ASSUMPTIONS:\n1. Jobs may have program errors\n2. PI interrupt for program errors introduced\n3. No physical separation between jobs\n4. Job outputs separated in output file by 2 blank lines\n5. Paging introduced, page table stored in real memory\n6. Program pages allocated one of 30 memory block using random number generator\n7. Load and run one program at a time\n8. Time limit, line limit, out-of-data errors introduced\n9. TI interrupt for time-out error introduced\n10. 2-line messages printed at termination\n\n\n### NOTATION\n\u003cbr\u003e\nM: memory\n\u003cbr\u003e\nIR: Instruction Register (4 bytes)\n\u003cbr\u003e\nIR [1,2]: Bytes 1,2 of IR/Operation Code\n\u003cbr\u003e\nIR [3, 4]: Bytes 3, 4 of IR/Operand Address\n\u003cbr\u003e\nM[\u0026]: Content of memory location \n\u003cbr\u003e\nIC: Instruction Counter Register (2 bytes)\n\u003cbr\u003e\nR: General Purpose Register (4 bytes)\n\u003cbr\u003e\nC: Toggle (1 byte)\n\u003cbr\u003e\nPTR: Page Table Register (4 bytes)\n\u003cbr\u003e\nPCB: Process Control Block (data structure)\n\u003cbr\u003e\nVA: Virtual Address\n\u003cbr\u003e\nRA: Real Address\n\u003cbr\u003e\nTTC: Total Time Counter\n\u003cbr\u003e\nLLC: Line Limit Counter\n\u003cbr\u003e\nTTL: Total Time Limit\n\u003cbr\u003e\nTLL: Total Line Limit\n\u003cbr\u003e\nEM: Error Message\n\u003cbr\u003e\n\n## License\nThis project is licensed under the [MIT License](https://github.com/ovuiproduction/Operating-System-Simulator/blob/main/LICENSE)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fovuiproduction%2Foperating-system-simulator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fovuiproduction%2Foperating-system-simulator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fovuiproduction%2Foperating-system-simulator/lists"}