{"id":13408197,"url":"https://github.com/pConst/basic_verilog","last_synced_at":"2025-03-14T12:32:23.370Z","repository":{"id":38619550,"uuid":"47992542","full_name":"pConst/basic_verilog","owner":"pConst","description":"Must-have verilog systemverilog modules","archived":false,"fork":false,"pushed_at":"2024-07-06T07:59:04.000Z","size":56836,"stargazers_count":1627,"open_issues_count":0,"forks_count":376,"subscribers_count":59,"default_branch":"master","last_synced_at":"2024-10-16T09:44:26.716Z","etag":null,"topics":["altera","debounce","delay","encoder","fifo","fpga","hls","pwm","spi-interface","spi-master","synchronizer","tcl","uart","uart-controller","uart-protocol","uart-receiver","uart-tx","uart-verilog","verilog","xilinx"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/pConst.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"license/88x31.png","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2015-12-14T18:09:40.000Z","updated_at":"2024-10-14T18:12:24.000Z","dependencies_parsed_at":"2024-07-06T09:04:25.660Z","dependency_job_id":null,"html_url":"https://github.com/pConst/basic_verilog","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pConst%2Fbasic_verilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pConst%2Fbasic_verilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pConst%2Fbasic_verilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pConst%2Fbasic_verilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/pConst","download_url":"https://codeload.github.com/pConst/basic_verilog/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243578643,"owners_count":20313881,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["altera","debounce","delay","encoder","fifo","fpga","hls","pwm","spi-interface","spi-master","synchronizer","tcl","uart","uart-controller","uart-protocol","uart-receiver","uart-tx","uart-verilog","verilog","xilinx"],"created_at":"2024-07-30T20:00:51.360Z","updated_at":"2025-03-14T12:32:18.345Z","avatar_url":"https://github.com/pConst.png","language":"Verilog","readme":null,"funding_links":[],"categories":["Projects and IPs","Libraries","Verilog"],"sub_categories":["Quora Topics"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FpConst%2Fbasic_verilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FpConst%2Fbasic_verilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FpConst%2Fbasic_verilog/lists"}