{"id":18868131,"url":"https://github.com/patricnilackshan/nano-processor-design","last_synced_at":"2026-02-08T13:08:26.101Z","repository":{"id":245240298,"uuid":"817665534","full_name":"patricnilackshan/Nano-Processor-Design","owner":"patricnilackshan","description":"Nano Processor capable of executing simple set of instructions: 4-bit Add/Subtract unit, 3-bit adder, 3-bit Program Counter, k-way b-bit multiplexers","archived":false,"fork":false,"pushed_at":"2024-07-04T09:32:46.000Z","size":1200,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-05-30T16:26:05.969Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Tcl","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/patricnilackshan.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2024-06-20T07:42:05.000Z","updated_at":"2025-03-04T15:20:02.000Z","dependencies_parsed_at":"2025-05-23T14:42:24.203Z","dependency_job_id":"ad151624-45d3-4156-8bac-96d88af8ff50","html_url":"https://github.com/patricnilackshan/Nano-Processor-Design","commit_stats":null,"previous_names":["patricnilackshan/nano-processor-design"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/patricnilackshan/Nano-Processor-Design","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/patricnilackshan%2FNano-Processor-Design","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/patricnilackshan%2FNano-Processor-Design/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/patricnilackshan%2FNano-Processor-Design/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/patricnilackshan%2FNano-Processor-Design/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/patricnilackshan","download_url":"https://codeload.github.com/patricnilackshan/Nano-Processor-Design/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/patricnilackshan%2FNano-Processor-Design/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":268265832,"owners_count":24222526,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-08-01T02:00:08.611Z","response_time":67,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-08T05:12:49.973Z","updated_at":"2026-02-08T13:08:26.060Z","avatar_url":"https://github.com/patricnilackshan.png","language":"Tcl","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Nano-Processor-Design\nNano Processor capable of executing simple set of instructions: 4-bit Add/Subtract unit , 3-bit adder, 3-bit Program Counter, k-way b-bit multiplexers\n\n\n| Instruction | Description | Format (12-bit instruction) |\n|-------------|-------------|-----------------------------|\n| MOVI R, d | Move immediate value d to register R, i.e., R ← d \u003cbr\u003eR ∈ [0, 7], d ∈ [0, 15] | 1 0 R R R 0 0 0 d d d d |\n| ADD Ra, Rb | Add values in registers Ra and Rb and store the result in Ra, i.e., Ra ← Ra + Rb \u003cbr\u003eRa, Rb ∈ [0, 7] | 0 0 Ra Ra Ra Rb Rb Rb 0 0 0 0 |\n| NEG R | 2’s complement of registers R, i.e., R ← −R \u003cbr\u003eR ∈ [0, 7] | 0 1 R R R 0 0 0 0 0 0 0 |\n| JZR R, d | Jump if value in register R is 0, i.e., \u003cbr\u003e\u0026nbsp;If R == 0 \u003cbr\u003e\u0026nbsp;\u0026nbsp;\u0026nbsp;PC ← d; \u003cbr\u003e\u0026nbsp;Else \u003cbr\u003e\u0026nbsp;\u0026nbsp;\u0026nbsp;PC ← PC + 1; \u003cbr\u003eR ∈ [0, 7], d ∈ [0, 7] | 1 1 R R R 0 0 0 0 d d d |\n\n\u003cbr\u003e\n\u003cbr\u003e\n\n---\n## Import the `NanoProcessor_G39` folder in Vivado and Run the Simulations or Test it on **BASYS3**.\n---\n\n\u003cimg align=\"right\" src=\"https://visitor-badge.laobi.icu/badge?page_id=patricnilackshan.Nano-Processor-Design\" /\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpatricnilackshan%2Fnano-processor-design","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpatricnilackshan%2Fnano-processor-design","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpatricnilackshan%2Fnano-processor-design/lists"}