{"id":24300721,"url":"https://github.com/paulopacitti/ascon-v","last_synced_at":"2026-04-25T05:40:26.108Z","repository":{"id":193771535,"uuid":"689460026","full_name":"paulopacitti/ascon-v","owner":"paulopacitti","description":"5️⃣ Ascon lightweight cryptographic algorithm implementation for improved performance on riscv64","archived":false,"fork":false,"pushed_at":"2024-02-22T00:27:38.000Z","size":12447,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-01-16T23:16:01.473Z","etag":null,"topics":["allwinner","allwinner-d1","ascon","cryptography","lightweight-cryptography","risc-v","riscv64"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/paulopacitti.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2023-09-09T21:57:46.000Z","updated_at":"2024-03-15T18:16:01.000Z","dependencies_parsed_at":"2024-02-22T01:31:55.196Z","dependency_job_id":null,"html_url":"https://github.com/paulopacitti/ascon-v","commit_stats":null,"previous_names":["paulopacitti/ascon-v"],"tags_count":6,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/paulopacitti%2Fascon-v","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/paulopacitti%2Fascon-v/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/paulopacitti%2Fascon-v/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/paulopacitti%2Fascon-v/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/paulopacitti","download_url":"https://codeload.github.com/paulopacitti/ascon-v/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":242213925,"owners_count":20090701,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["allwinner","allwinner-d1","ascon","cryptography","lightweight-cryptography","risc-v","riscv64"],"created_at":"2025-01-16T23:16:08.659Z","updated_at":"2026-04-25T05:40:26.054Z","avatar_url":"https://github.com/paulopacitti.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"# ascon-v 5️⃣\nAscon lightweight cryptographic algorithm implementation for improved performance on RISC-V. Tested on the Allwinner D1 processor. My bachelor's thesis at [UNICAMP's Institute of Computing](https://ic.unicamp.br/en/).\n\n![](cover.jpg)\n\n## Abstract\n\n\u003e RISC-V is a promising ISA and soon will be the architecture of many chips, specially embedded systems. It's necessary to guarantee that applications that run in systems designed with RISC-V will be at the same time secure and cryptographically fast. The NIST Lightweight Cryptography competition selected the finalist: Ascon, a family of cryptography algorithms designed to run in devices with low computational power. This research explores the Ascon family of algorithms on the RISC-V 64-bit architecture, analysing the Ascon permutation and the Ascon-128 algorithm, and whether it's possible to optimize it for `riscv64`, proposing a new technique regarding the decryption implementation. The implementation developed in this research was benchmarked in the Allwinner D1 chip, a RISC-V 64-bit 1 GHz single-issue CPU supporting the RV64GC ISA, and compared with other implementations. Finally, it's discussed that new microarchitectures, and, the future of the RISC-V ISA with new instructions extensions recently ratified, could improve the performance of the Ascon family of algorithms and other cryptographic algorithms.\n\n## Structure\n\n- `lib/`: libraries\n- `ref/`: reference [implementation](https://github.com/ascon/ascon-c)\n- `opt64`: implementation optimized for 64-bit architectures, made by the Ascon team.\n- `src/`: source code for `ascon-v`, optmized implementation for `rv64imac`\n- `benchmark/`: performance benchmark comparing the different implmentations\n- `tests/`: tests for `ascon-v`\n- `tex/`: source files for TeX used for building the essay PDF. The research paper is written in the `tex/main.pdf` file\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpaulopacitti%2Fascon-v","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpaulopacitti%2Fascon-v","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpaulopacitti%2Fascon-v/lists"}