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PLEASE USE IT WITH CAUTION\n\n\n- Use Xilinx power estimator (XPE) tool first. It will estimate currents\nand dissipated heat results.\n- Make sure you dont overload power system of your device. FPGA will refuse\nto boot up if VCCINT power rail voltage got depleted. See\nhttps://forums.xilinx.com/t5/Configuration/Error-Labtools-27-3165-End-of-startup-status-LOW/td-p/737029\n- Control temperatures of FPGA chip and power supply chains during the test.\n- On Ultarscale chips, use SYSMON for monitoring.\n- Dont exceed recommended FPGA Tj. Additional active cooling can be beneficial.\n- Increase load iteratively.\n\n// 1. Loading power by SRLs (shift registers based on LUTs)\n// The simplest way to load Xilinx FPGA is to infer SRL16 or SRL32  primitives\n\n// 2. Loading power by integrated block RAM blocks\n\n// 3. Loading power by registers\n// Dont use this feature untill you cant drain enough power by previous options\n// because this step takes A LOT of time to synthesize and implement\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpconst%2Fxilinx_max_power","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpconst%2Fxilinx_max_power","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpconst%2Fxilinx_max_power/lists"}