{"id":21040562,"url":"https://github.com/pixelspark/rv32jit","last_synced_at":"2026-04-21T20:02:32.111Z","repository":{"id":136773363,"uuid":"580156284","full_name":"pixelspark/rv32jit","owner":"pixelspark","description":"A RISC-V (rv32imc) assembler for JITing on the ESP32","archived":false,"fork":false,"pushed_at":"2023-11-01T18:30:56.000Z","size":79,"stargazers_count":6,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2026-01-13T18:53:56.733Z","etag":null,"topics":["esp32","esp32-c3","risc-v","riscv32","riscv32im","rust"],"latest_commit_sha":null,"homepage":"","language":"Rust","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/pixelspark.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-12-19T21:24:26.000Z","updated_at":"2025-11-27T11:20:42.000Z","dependencies_parsed_at":null,"dependency_job_id":"f3b47021-80b8-4542-94e8-50940502e706","html_url":"https://github.com/pixelspark/rv32jit","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/pixelspark/rv32jit","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pixelspark%2Frv32jit","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pixelspark%2Frv32jit/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pixelspark%2Frv32jit/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pixelspark%2Frv32jit/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/pixelspark","download_url":"https://codeload.github.com/pixelspark/rv32jit/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pixelspark%2Frv32jit/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":32108187,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-04-21T11:25:29.218Z","status":"ssl_error","status_checked_at":"2026-04-21T11:25:28.499Z","response_time":128,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["esp32","esp32-c3","risc-v","riscv32","riscv32im","rust"],"created_at":"2024-11-19T13:47:10.341Z","updated_at":"2026-04-21T20:02:32.078Z","avatar_url":"https://github.com/pixelspark.png","language":"Rust","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RISC-V 32-bit JIT\n\nAn assembler for JIT compilation for use on ESP32-C3 (rv32imc)\n\n## Setting up the environment\n\n```\nrustup toolchain install nightly\nrustup target add riscv32imc-unknown-none-elf\ncargo install ldproxy\ncargo install cargo-espflash\n```\n\n## Building\n\n```bash\ncargo build --release\n```\n\nTo flash and run:\n\n```bash\ncargo espflash --release --monitor\n```\n\nIf you get a certificate error on macOS:\n\n```bash\ncurl \"https://ccadb-public.secure.force.com/mozilla/IncludedRootsPEMTxt?TrustBitsInclude=Websites\" \u003e IncludedRootsPEM.txt\nSSL_CERT_FILE=$(pwd)/IncludedRootsPEM.txt cargo build\n```\n\nTo test locally (replace `aarch64-apple-darwin` with your system's target triple, use `rustup target list` to find installed targets):\n\n```bash\ncargo run --example assemble --target aarch64-apple-darwin -- ~/Desktop/test2.bin\n```\n\nThe above will write a binary that you can upload in e.g. [this disassembler](https://jborza.com/riscvdasm/).\n\n## Testing\n\n```bash\ncd rv32assembler\ncargo test --target aarch64-apple-darwin\n```\n\n## Usage\n\n```rust\nfn test_jit_simple() {\n\tlet mut f = Fragment::new();\n\tf.addi(Register::A0, Register::A0, 42);\n\tf.ret();\n\tlet program = JitFunction::from(\u0026f);\n\tlet s = unsafe { program.call(88) };\n\tassert_eq!(s, 88 + 42);\n}\n```\n\nIf you want to use this crate in your own project, be sure to set the following option in `sdkconfig.defaults`:\n\n```toml\n# Required to allow JIT\nCONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n\n```\n\n## References\n\nUseful reference material:\n\n- [RISC-V reference card](https://github.com/jameslzhu/riscv-card/blob/master/riscv-card.pdf)\n- [RV32I Base Integer Instruction Set, Version 2.1](https://five-embeddev.com/riscv-isa-manual/latest/rv32.html#)\n- [Online RISC-V assembler](https://riscvasm.lucasteske.dev/#)\n- [Online RISC-V disassembler](https://jborza.com/riscvdasm/)\n- [Another RISC-V assembler in Rust](https://github.com/michaelmelanson/riscy)\n- [Berkeley CS61C RISC-V instruction formats lecture](https://inst.eecs.berkeley.edu/~cs61c/resources/su18_lec/Lecture7.pdf)\n- [Sign extension](https://en.wikipedia.org/wiki/Sign_extension)\n\nTo create a binary file from \"[1, 2, 3]\" debug output:\n\n```js\nconst fs = require(\"fs\");\nfs.writeFileSync(\"foo.bin\", Buffer.from([1, 2, 3]));\n```\n\n## License\n\n[MIT](./LICENSE)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpixelspark%2Frv32jit","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpixelspark%2Frv32jit","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpixelspark%2Frv32jit/lists"}