{"id":13649320,"url":"https://github.com/pnnl/OpenCGRA","last_synced_at":"2025-04-22T14:31:19.622Z","repository":{"id":41360087,"uuid":"296382149","full_name":"pnnl/OpenCGRA","owner":"pnnl","description":"OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.","archived":false,"fork":false,"pushed_at":"2023-03-02T02:08:05.000Z","size":431,"stargazers_count":145,"open_issues_count":4,"forks_count":24,"subscribers_count":8,"default_branch":"master","last_synced_at":"2025-04-06T01:51:11.188Z","etag":null,"topics":["open-source-hardware","opencgra"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/pnnl.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2020-09-17T16:27:23.000Z","updated_at":"2025-03-19T04:10:32.000Z","dependencies_parsed_at":"2024-01-17T15:08:39.857Z","dependency_job_id":null,"html_url":"https://github.com/pnnl/OpenCGRA","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pnnl%2FOpenCGRA","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pnnl%2FOpenCGRA/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pnnl%2FOpenCGRA/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pnnl%2FOpenCGRA/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/pnnl","download_url":"https://codeload.github.com/pnnl/OpenCGRA/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258930,"owners_count":21401000,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["open-source-hardware","opencgra"],"created_at":"2024-08-02T01:04:56.798Z","updated_at":"2025-04-22T14:31:14.603Z","avatar_url":"https://github.com/pnnl.png","language":"Verilog","funding_links":[],"categories":["Verilog","Accelerators"],"sub_categories":[],"readme":"\u003cpre\u003e\n==========================================\n\n  ____                _____________  ___ \n / __ \\___  ___ ___  / ___/ ___/ _ \\/ _ |\n/ /_/ / _ \\/ -_) _ \\/ /__/ (_ / , _/ __ |\n\\____/ .__/\\__/_//_/\\___/\\___/_/|_/_/ |_|\n    /_/                                  \n\n==========================================\n\u003c/pre\u003e\n[![Build Status](https://travis-ci.com/pnnl/OpenCGRA.svg?token=yazoBFLC1ynpzdD4wAEP\u0026branch=master)](https://travis-ci.com/github/pnnl/OpenCGRA)\n\nOpenCGRA is a parameterizable and powerful CGRA (Coarse-Grained Reconfigurable Arrays) generator to generate synthesizable Verilog for different CGRAs based on user-specified configurations (e.g., CGRA size, type of the computing units in each tile, communication connection, etc.). OpenCGRA uses modular design and standardized interfaces between modules. The configurability and extensibility are maximized by its parametrization system to fit in various research and industrial needs.\n\nDocker\n--------------------------------------------------------\nThe docker image is available [here](https://hub.docker.com/layers/cgra/cgra-flow/demo/images/sha256-7ca327d24f555376d91cba6fa30e3fbaa4a4c0d4053a82ac9059c374a3dee5bd?context=repo).\n\nRelated publications\n--------------------------------------------------------------------------\n\n- Cheng Tan, et al. _“AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators.”_ The 2021 Design, Automation \u0026 Test in Europe Conference, Grenoble, France. (DATE-21) February 1-5, 2021.\n- Cheng Tan, et al. _\"ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing.\"_ IEEE Transactions on Parallel and Distributed Systems (TPDS-21).\n- Cheng Tan, et al. _\"OpenCGRA: An Open-Source Framework for Modeling, Testing, and Evaluating CGRAs.\"_ The 38th IEEE International Conference on Computer Design. (ICCD-20), Oct 2020.\n\n\nLicense\n--------------------------------------------------------------------------\n\nOpenCGRA is offered under the terms of the Open Source Initiative BSD 3-Clause License. More information about this license can be found here:\n\n  - http://choosealicense.com/licenses/bsd-3-clause\n  - http://opensource.org/licenses/BSD-3-Clause\n\n\nInstallation\n--------------------------------------------------------\n\nOpenCGRA requires Python3.7 (note that \u003c2.x and \u003e3.7 do not work for now) and has the following additional prerequisites:\n\n - graphviz, verilator\n - git, Python headers, and libffi\n - virtualenv\n - PyMTL3\n\nThe steps for installing these prerequisites and OpenCGRA on a fresh Ubuntu\ndistribution are shown below. They have been tested with Ubuntu Trusty\n14.04 ~ 20.04.\n\n### Install python3\n\n```\n % sudo apt-get install python3.7\n```\n\n### Install graphviz\n\n```\n % sudo apt-get install -y graphviz\n```\n\n### Install Verilator\n\n[Verilator][4] is an open-source toolchain for compiling Verilog RTL\nmodels into C++ simulators. OpenCGRA uses Verilator for Verilog import.\n\n```\n $ sudo apt-get install git make autoconf g++ libfl-dev bison\n $ mkdir -p ${HOME}/src\n $ cd ${HOME}/src\n $ wget http://www.veripool.org/ftp/verilator-4.036.tgz\n $ tar -xzvf verilator-4.036.tgz\n $ cd verilator-4.036\n $ ./configure\n $ make\n $ sudo make install\n```\n\n [4]: http://www.veripool.org/wiki/verilator\n\n### Install git, Python headers, and libffi\n\nWe need to install the Python headers and libffi in order to be able to\ninstall the cffi Python package. cffi provides an elegant way to call C\nfunctions from Python, and PyMTL uses cffi to call C code generated by\nVerilator. We will use git to grab the PyMTL source. The following\ncommands will install the appropriate packages:\n\n```\n % sudo apt-get install git python-dev libffi-dev\n```\n\n### Create virtual environment\n\nWhile not strictly necessary, we strongly recommend using [virtualenv][5]\nto install PyMTL3 and the Python packages that PyMTL3 depends on.\nvirtualenv enables creating isolated Python environments. The following\ncommands will create and activate the virtual environment:\n\n```\n % python3 -m venv ${HOME}/venv\n % source ${HOME}/venv/bin/activate\n```\n\n [5]: https://virtualenv.pypa.io/en/latest/\n\n### Install PyMTL3 and Python requirements\n\n```\n % pip install git+https://github.com/tancheng/pymtl3.git\n % pip install --upgrade pip setuptools twine\n % pip install hypothesis\n % pip list\n```\n\n### Clone OpenCGRA repo\n\nWe can now use git to clone the OpenCGRA repo.\n\n```\n % mkdir -p ${HOME}/cgra\n % cd ${HOME}/cgra\n % git clone https://github.com/pnnl/OpenCGRA.git\n```\n\n### Run an example to generate Verilog\n\nIn [folder](https://github.com/pnnl/OpenCGRA/tree/master/cgra/translate), just type:\n\n```\n % pytest --tb=short -sv CGRARTL_test.py\n```\n\nWhen you're done testing/developing, you can deactivate the virtualenv::\n\n```\n % deactivate\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpnnl%2FOpenCGRA","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpnnl%2FOpenCGRA","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpnnl%2FOpenCGRA/lists"}