{"id":15395166,"url":"https://github.com/postspectacular/cmsis-svd-srcgen","last_synced_at":"2025-04-14T10:35:25.954Z","repository":{"id":47456977,"uuid":"48288423","full_name":"postspectacular/cmsis-svd-srcgen","owner":"postspectacular","description":"Extensible ARM CMSIS SVD spec based, multi-language source code generator","archived":false,"fork":false,"pushed_at":"2016-01-01T17:48:21.000Z","size":13,"stargazers_count":18,"open_issues_count":0,"forks_count":1,"subscribers_count":6,"default_branch":"master","last_synced_at":"2025-03-27T23:44:24.928Z","etag":null,"topics":["arm","cmsis","codegen","svd"],"latest_commit_sha":null,"homepage":null,"language":"XSLT","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/postspectacular.png","metadata":{"files":{"readme":"README.org","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2015-12-19T16:06:10.000Z","updated_at":"2022-12-21T18:35:36.000Z","dependencies_parsed_at":"2022-08-28T09:03:33.553Z","dependency_job_id":null,"html_url":"https://github.com/postspectacular/cmsis-svd-srcgen","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/postspectacular%2Fcmsis-svd-srcgen","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/postspectacular%2Fcmsis-svd-srcgen/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/postspectacular%2Fcmsis-svd-srcgen/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/postspectacular%2Fcmsis-svd-srcgen/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/postspectacular","download_url":"https://codeload.github.com/postspectacular/cmsis-svd-srcgen/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248863470,"owners_count":21174007,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["arm","cmsis","codegen","svd"],"created_at":"2024-10-01T15:26:30.080Z","updated_at":"2025-04-14T10:35:25.934Z","avatar_url":"https://github.com/postspectacular.png","language":"XSLT","funding_links":[],"categories":[],"sub_categories":[],"readme":"* cmsis-svd-srcgen\n\nConvert ARM CMSIS SVD specs (processor peripherals, register \u0026\nbitfields) into source code for different languages.\n\nCurrently supported target languages are: Asm (GCC flavor), C and\nClojure. Other languages can be easily supported by defining a new\nXSLT stub file with language specific configuration/formatting.\n\nProject inspired by: [[https://github.com/posborne/cmsis-svd][posborne/cmsis-svd]]\n\n** Usage\n\n#+BEGIN_SRC shell\n./convert asm|c|clj svd-file \u003e output-file\n\n# filtered output via \"only\" and \"excl\" params\n# only includes given peripheral IDs or excludes these\n./convert lang svd only=PERIPH1,PERIPH2... \u003e output\n./convert lang svd excl=PERIPH1,PERIPH2... \u003e output\n#+END_SRC\n\n** Requirements\n\n- [[http://www.saxonica.com/download/opensource.xml][SAXON-HE 9.7+]] (or another XSLT2.0 capable processor)\n- Java 7+\n\nYou'll also need to download an SVD file for your CPU. A list of SVDs\nfor all manufacturers is here (under CMSIS-SVD tab on that page,\nrequires registration):\n\nhttp://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php\n\nSTM32 CPU specs can be found here:\n\nhttps://cmsis.arm.com/vendor/stmicroelectronics/\n\n** Output format\n\nDepending on included details in SVD file, the following definitions\nare generated:\n\n- peripheral base registers\n- peripheral sub-registers (abs address and offset)\n- register reset value\n- register bitfield shift offset \u0026 mask\n\nSome SVD specs define derived periphals. The extractor supports this\nfeature and generates a replicated register set (with correct address\noffsets) for each derived definition.\n\n*** Naming convention\n\nThe overall generate symbol formats follow these patterns (words\nprefixed with =$= are variable):\n\n#+BEGIN_SRC\n$PERIPHERAL baseaddress\n$PERIPHERAL_$REGISTER baseaddress + registeroffset\n$PERIPHERAL_$REGISTER_OFFSET registeroffset\n$PERIPHERAL_$REGISTER_RESET resetvalue (if given)\n$PERIPHERAL_$REGISTER_$FIELD xx (absolute bit mask, e.g. \"0xf \u003c\u003c 24\")\n$PERIPHERAL_$REGISTER_$FIELD_SHIFT xx (bit position)\n#+END_SRC\n\nBecause different symbols are defined for each bitfield item, the\ngenerated files can become quite large (10k+ lines). Use the device\nfiltering options to reduce file size and only include the ones used\nfor your project.\n\n*** Example output\n**** C\n\n#+BEGIN_SRC c\n/****************************************************************\n * STM32F401x SVD peripherals \u0026 registers\n * generated @ 2015-12-23 13:30:59\n * \n * DO NOT EDIT! This file was autogenerated with:\n * http://github.com/postspectacular/cmsis-svd-srcgen\n ****************************************************************/\n\n#ifndef _CMSIS_SVD_H\n#define _CMSIS_SVD_H\n\n/****************************************************************\n * General-purpose I/Os (derived from GPIOH)\n ****************************************************************/\n#define GPIOD 0x40020c00\n#define GPIOD_MODER (GPIOD + 0x0) // GPIO port mode register\n#define GPIOD_MODER_OFFSET 0x0\n#define GPIOD_MODER_RESET 0x00000000\n#define GPIOD_MODER_MODER15 (0x3 \u003c\u003c 30)\n#define GPIOD_MODER_MODER15_SHIFT 30\n#define GPIOD_MODER_MODER14 (0x3 \u003c\u003c 28)\n#define GPIOD_MODER_MODER14_SHIFT 28\n...\n\n/****************************************************************\n * Nested Vectored Interrupt Controller\n ****************************************************************/\n#define NVIC 0xe000e000\n#define NVIC_ICTR (NVIC + 0x4) // Interrupt Controller Type Register\n#define NVIC_ICTR_OFFSET 0x4\n#define NVIC_ICTR_RESET 0x00000000\n#define NVIC_ICTR_INTLINESNUM 0xf\n#define NVIC_ICTR_INTLINESNUM_SHIFT 0\n#define NVIC_STIR (NVIC + 0xf00) // Software Triggered Interrupt Register\n#define NVIC_STIR_OFFSET 0xf00\n#define NVIC_STIR_RESET 0x00000000\n#define NVIC_STIR_INTID 0x1ff\n#define NVIC_STIR_INTID_SHIFT 0\n...\n#+END_SRC\n\n** Contributors\n\n| *Name*          | *Role*                          | *Website*                                 |\n|-----------------+---------------------------------+-------------------------------------------|\n| [[mailto:k@thi.ng][Karsten Schmidt]] | initiator \u0026 principal developer | http://postspectacular.com, http://thi.ng |\n\n** License\n\n(c) 2015 Karsten Schmidt, this project is open source and licensed under the [[http://www.apache.org/licenses/LICENSE-2.0][Apache Software License 2.0]].\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpostspectacular%2Fcmsis-svd-srcgen","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpostspectacular%2Fcmsis-svd-srcgen","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpostspectacular%2Fcmsis-svd-srcgen/lists"}