{"id":20875579,"url":"https://github.com/priyanshscpp/ECE907-Single-Port-RAM-VLSI-CourseWork","last_synced_at":"2025-05-12T15:31:32.516Z","repository":{"id":239218626,"uuid":"798904725","full_name":"priyanshscpp/ECE907-Single-Port-RAM-VLSI-CourseWork","owner":"priyanshscpp","description":"Single-Port RAM Implementation","archived":false,"fork":false,"pushed_at":"2024-06-21T10:26:03.000Z","size":7,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-02-26T22:13:56.458Z","etag":null,"topics":["amd64","amdgpu","vhdl","xilinix"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/priyanshscpp.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-05-10T18:14:36.000Z","updated_at":"2024-06-21T10:28:11.000Z","dependencies_parsed_at":null,"dependency_job_id":"1df23aa5-1bae-4058-b28c-e23b3c2608a6","html_url":"https://github.com/priyanshscpp/ECE907-Single-Port-RAM-VLSI-CourseWork","commit_stats":null,"previous_names":["priyanshuhbti/single_port-ram","priyanshscpp/ece907-single-port-ram-vlsi-coursework"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/priyanshscpp%2FECE907-Single-Port-RAM-VLSI-CourseWork","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/priyanshscpp%2FECE907-Single-Port-RAM-VLSI-CourseWork/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/priyanshscpp%2FECE907-Single-Port-RAM-VLSI-CourseWork/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/priyanshscpp%2FECE907-Single-Port-RAM-VLSI-CourseWork/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/priyanshscpp","download_url":"https://codeload.github.com/priyanshscpp/ECE907-Single-Port-RAM-VLSI-CourseWork/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253765884,"owners_count":21960810,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["amd64","amdgpu","vhdl","xilinix"],"created_at":"2024-11-18T06:47:04.180Z","updated_at":"2025-05-12T15:31:31.790Z","avatar_url":"https://github.com/priyanshscpp.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"                 \n# Single-Port RAM Implementation\n\nThis repository provides a Verilog implementation of a single-port Random Access Memory (RAM) module. A single-port RAM allows access to one memory location at a time for either reading or writing data.\n \n## Getting Started\n\nClone the Repository:\n\nBash\ngit clone https://github.com/priyanshuhbti/single-port-ram.git\nUse code with caution.\ncontent_copy\n\nSynthesis and Simulation (Optional):-   \n\nIf you intend to synthesize or simulate the RAM design, ensure you have the necessary hardware description language (HDL) tools installed and configured. The specific steps will vary depending on your tools.\n \n## Built With\n\nThe single_port_ram.v file will typically contain the following sections:\n\nParameterization: Allow customization of data and address widths.\n\nMemory Declaration: Create a register array to store the RAM data.\n\nRead Logic: Implement read operation based on the address and enable signals.\n\nWrite Logic: Implement write operation based on the address, write enable, and data input signals.\n\nOutput Logic: Assign the appropriate data (read or written) to the data_out port.\n\n- [VHDL](https://www.contributor-covenant.org/)\n- [Xilinx-AMD](https://creativecommons.org/)\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpriyanshscpp%2FECE907-Single-Port-RAM-VLSI-CourseWork","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpriyanshscpp%2FECE907-Single-Port-RAM-VLSI-CourseWork","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpriyanshscpp%2FECE907-Single-Port-RAM-VLSI-CourseWork/lists"}