{"id":23119544,"url":"https://github.com/programmerdan/digica","last_synced_at":"2025-06-11T17:02:35.116Z","repository":{"id":12681906,"uuid":"15354025","full_name":"ProgrammerDan/digica","owner":"ProgrammerDan","description":"This is a rather older project that allows circuit simulation.","archived":false,"fork":false,"pushed_at":"2013-12-21T07:14:59.000Z","size":148,"stargazers_count":1,"open_issues_count":0,"forks_count":2,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-04-04T02:41:37.794Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ProgrammerDan.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2013-12-21T04:53:30.000Z","updated_at":"2017-08-16T02:02:22.000Z","dependencies_parsed_at":"2022-09-02T11:02:06.364Z","dependency_job_id":null,"html_url":"https://github.com/ProgrammerDan/digica","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ProgrammerDan/digica","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ProgrammerDan%2Fdigica","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ProgrammerDan%2Fdigica/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ProgrammerDan%2Fdigica/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ProgrammerDan%2Fdigica/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ProgrammerDan","download_url":"https://codeload.github.com/ProgrammerDan/digica/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ProgrammerDan%2Fdigica/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":259301676,"owners_count":22836975,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-12-17T05:39:17.282Z","updated_at":"2025-06-11T17:02:35.090Z","avatar_url":"https://github.com/ProgrammerDan.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"digica\n======\n\nDigital Circuit Analyzer\nby Daniel Boston (ProgrammerDan)\n\nApril 19, 2005\n\nFor cs1210 (C++ Programming class)\n\nClearly this wasn't my first coding rodeo, and I wanted to prove as much to \nthe prof so I could skip any other intro classes.\n\nIntroduction\n------------\n\nThis is a rather older project that allows circuit simulation.\n\nIt's almost-but-not-quite ready to Make -- be sure to modify the makefile\nto point to your local installation of EzWindows and X11 -- or modify to use\na Windows build of EzWindows if preferred. If you do this, please fork my code\nand send me the results!\n\nThe most complete reference to EzWindows (the Devon Lockwood version) I could\nfind while preparing this archive is:\n\n[http://www.cs.virginia.edu/c++programdesign/software/]\n(http://www.cs.virginia.edu/c++programdesign/software/)\n\nMajor kudos to [Dr. Keith Shomper]\n(http://www.cedarville.edu/Academics/Engineering-and-Computer-Science/Faculty/Shomper-Keith.aspx)\nfor his excellent lessons on C and C++ and for putting up with me during\ncs1210.\n\nInstructions\n------------\n\n1. Modify makefile to fit your system (see Introduction)\n2. Run Make\n3. Execute digica\n4. Follow program interactive instructions\n\nCreating a Circuit\n------------------\n\nSo, I must confess, it's been the better part of a decade since I've even\nlooked at this code. However, the format for the input file is remarkably\nstraightforward, so I'll do my best to describe it here.\n\n### Circuit File\n\nNaming: `\u003cfilename\u003e`.txt\n\n_Key Concepts:_\n* Circuits are larger constructs that deal with signal propagation through\nlogic gates. \n* Circuits are composed of pads (input and output), logic gates,\nand wires. \n* To help visualize, pads are always at the beginning and end of a\ncircuit (although outputs can feed back into the circuit), gates sit inbetween\nthe sets of pads, and wires connect every element. \n* Both the \"input\" and \"output\" wire of a pad or gate is referenced by an \ninteger, and whether to use the \"input\" or \"output\" side of the wire is \ndetermined contextually (I think!).\n* The circuit file is exclusively concerned with setting up the circuit -- it\nallows specification of propogation delays, complex gate logic with feedback,\nand more, but it does not allow the specification of input sets. That will be\nin the next section dealing with the Vector file.\n\n_File Elements:_\n* CIRCUIT `\u003clabel\u003e`  --  Signals the beginning of a new circuit. Every \ncircuit file should start this this. Label must not be skipped.\n* INPUT `\u003cpad_id\u003e` `\u003cwire_id\u003e`  --  Generates a new input pad. Pad_id is \nrequired (for display) and wire_id must be an integer and unique within \nthe file.\n* OUTPUT `\u003cpad_id\u003e` `\u003cwire_id\u003e`  --  Generates a new output pad. Pad_id is \nrequired (for display) and wire_id must be an integer and unique within \nthe file.\n* `\u003c1-gate\u003e` `\u003cdelay\u003e` `\u003cin-wire\u003e` `\u003cout-wire\u003e` -- Single-input gate. Delay \nspecifies signal propagation delay - the length of time it takes the input \nsignal to reach the output, in nanoseconds (must be greater than 0 - if \nnegative or zero, gets set to 1ns). In-wire specifies which wire to tap for \ninput, out-wire specifies which wire to fill with output. Valid values \nof `\u003c1-gate\u003e`:\n * NOT -- Logical NOT gate: if the input is true, the output becomes false\n * INV -- Same.\n * INVERTER -- Same.\n* `\u003c2-gate\u003e` `\u003cdelay\u003e` `\u003cin-wire-1\u003e` `\u003cin-wire-2\u003e` `\u003cout-wire\u003e` -- Two-input\ngate. Delay specifies signal propogation delay. In-wire-1 and In-wire-2 specify the inputs to the gate, and out-wire specifies which wire to fill with output.\nValid values of `\u003c2-gate\u003e`:\n * OR -- Logical OR gate: if either input is true, the output becomes true\n(after delay).\n * AND -- Logical AND gate: if both inputs are true, the output becomes true\n * NAND -- Logical NOT-AND gate: if any input is false, the output becomes true\n * NOR -- Logical NOT-OR gate: if none of the inputs are true, the output \nbecomes true\n * XOR -- Logical Exclusive-OR gate: if exclusively one input is true, the \noutput becomes true\n * XNOR -- Logical Exclusive-NOR gate: if both inputs are the same value, the \noutput becomes true\n\n_Example:_\n```\nCIRCUIT Circuit1\nINPUT   A    1\nINPUT   B    3\nINPUT   C    4\nOUTPUT  D    5\nOUTPUT  E    6\nNOT     2ns  1   2\nAND     3ns  2   3   5\nOR      3ns  4   5   6\n```\n\n### Vector File\n\nNaming: `\u003cfilename\u003e`_v.txt\n\n_Key Concepts:_\n* The vector file is basically a playbook for sending signals into the Circuit.\nIt specifies a \"program\" to execute against the inputs, which will naturally\ncause some kind of activity inside the circuit. \n* All the gates described above support ternary logic (just for fun) values \nwhich are -- low (0), high (1), and indeterminate (2, X or x). \n* Thus, inputs can be set to any of these values, and as the circuit \n\"executes\" the inputs will cycle through whatever values are specified in \nthe vector file.\n* Once a value is specified on an input, it remains that way until a new\nvalue is specified.\n\n_File Elements:_\n* VECTOR `\u003clabel\u003e`  --  Signals the beginning of a new vector. Every \nvector file should start this this. Label must not be skipped.\n* INPUT `\u003cpad_id\u003e` `\u003ctrans_time\u003e` `\u003cstate\u003e` -- Indicates a new scheduled state\ntransition at an input pad. All inputs by default start as indeterminate, so\nit's a good idea to explicitly specify all inputs at trans_time 0. Of course,\npad_id must be defined in the Circuit file, trans_time must be 0 or greater,\nand state must be one of:\n * 0  --  Low (false)\n * 1  --  High (true)\n * 2  --  Indeterminate (???)\n * X  --  Indeterminate (???)\n * x  --  Indeterminate (???)\n\n_Example:_\n```\nVECTOR Circuit1\nINPUT A  0  0\nINPUT B  0  1\nINPUT C  0  0\nINPUT C  4  1\nINPUT A  6  1\nINPUT B  9  0\n```\n\nConclusion\n----------\n\nTurns out you can create some rather complex circuits with this relatively\nsimple application. Check out the circuits/ folder for a number of examples,\nand some counter-examples, demonstrating what this code can do, including\nflip-flops, muxers, adders, and more.\n\nI hope you enjoy! Contact me at ProgrammerDan@gmail.com or [ProgrammerDan]\n(https://twitter.com/ProgrammerDan).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fprogrammerdan%2Fdigica","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fprogrammerdan%2Fdigica","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fprogrammerdan%2Fdigica/lists"}