{"id":19711997,"url":"https://github.com/programmerjake/rv32","last_synced_at":"2026-03-04T11:31:41.732Z","repository":{"id":70478288,"uuid":"126104309","full_name":"programmerjake/rv32","owner":"programmerjake","description":"RISC-V 32-bit processor that runs a 2.5D maze game; Built for CPTR380 Winter of 2018 at Walla Walla University","archived":false,"fork":false,"pushed_at":"2018-11-28T07:54:55.000Z","size":150,"stargazers_count":7,"open_issues_count":0,"forks_count":1,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-02-27T19:58:46.623Z","etag":null,"topics":["fpga","maze-game","raycasting","risc-v","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/programmerjake.png","metadata":{"files":{"readme":"ReadMe.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-03-21T01:17:48.000Z","updated_at":"2024-11-05T09:35:31.000Z","dependencies_parsed_at":"2023-02-24T02:31:04.538Z","dependency_job_id":null,"html_url":"https://github.com/programmerjake/rv32","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/programmerjake/rv32","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/programmerjake%2Frv32","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/programmerjake%2Frv32/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/programmerjake%2Frv32/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/programmerjake%2Frv32/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/programmerjake","download_url":"https://codeload.github.com/programmerjake/rv32/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/programmerjake%2Frv32/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30078985,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-04T08:01:56.766Z","status":"ssl_error","status_checked_at":"2026-03-04T08:00:42.919Z","response_time":59,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","maze-game","raycasting","risc-v","verilog"],"created_at":"2024-11-11T22:14:47.816Z","updated_at":"2026-03-04T11:31:41.705Z","avatar_url":"https://github.com/programmerjake.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# 32-bit RISC-V processor design\n\nImplements RV32I instruction set except for interrupts and some CSRs.\n\nWarning: CSR and system instructions weren't really tested so may not work properly\n\nDefault software runs a 2.5D maze game through the VGA port, using SW2 and SW3 to turn and move.\n\nImplemented CSRs:\n- cycle/cycleh -- doesn't count\n- time/timeh -- doesn't count\n- instret/instreth -- doesn't count\n- mvendorid\n- marchid\n- mimpid\n- misa -- ignores writes\n- mstatus -- all but mpie and mie are hardwired\n- mie -- all but meie, mtie, and msie are hardwired\n- mtvec -- hardwired to 0x10040\n- mscratch\n- mepc\n- mcause\n- mip -- ignores writes\n\n- used FPGA: ChinaQMTECH's QM_XC6SLX16_DDR3 board with the vga output board. [Docs](https://raw.githubusercontent.com/ChinaQMTECH/QM_XC6SLX16_DDR3/master/QM_XC6SLX16_DDR3_V02.zip) [archived on archive.org](http://web.archive.org/web/20180321000346/https://raw.githubusercontent.com/ChinaQMTECH/QM_XC6SLX16_DDR3/master/QM_XC6SLX16_DDR3_V02.zip)\n- used programmer: Digilent's Hs2 JTAG programmer\n\n## Building (On Ubuntu 16.04)\nRequires Xilinx's ISE v. 14.7 to be installed in /opt/Xilinx (just leave the default installation directory)\n\n    sudo apt-get install git g++ autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev\n    sudo mkdir /opt/riscv\n    sudo chown $USER /opt/riscv # so you don't need root when building; you can change back after building riscv-gnu-toolchain\n    git clone --recursive https://github.com/riscv/riscv-gnu-toolchain.git\n    export PATH=/opt/riscv/bin:\"$PATH\"\n    cd riscv-gnu-toolchain\n    ./configure --prefix=/opt/riscv --with-arch=rv32i\n    make\n    sudo chown -R root:root /opt/riscv # change owner back to root as the compiler is finished installing\n    cd ..\n    git clone https://github.com/programmerjake/rv32.git\n    cd rv32/software\n    make\n    cd ..\n    # at this point the built bitstream is in output.bit\n    djtgcfg prog -d JtagHS2 -i 0 -f output.bit # program the FPGA\n\n## Simulating using Icarus Verilog\nDoesn't require Xilinx's ISE or Digilent's programmer\n\n    sudo apt-get install git g++ autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev\n    sudo mkdir /opt/riscv\n    sudo chown $USER /opt/riscv # so you don't need root when building; you can change back after building riscv-gnu-toolchain\n    git clone --recursive https://github.com/riscv/riscv-gnu-toolchain.git\n    export PATH=/opt/riscv/bin:\"$PATH\"\n    cd riscv-gnu-toolchain\n    ./configure --prefix=/opt/riscv --with-arch=rv32i\n    make\n    sudo chown -R root:root /opt/riscv # change owner back to root as the compiler is finished installing\n    cd ..\n    git clone https://github.com/programmerjake/rv32.git\n    cd rv32/software\n    make ram0_byte0.hex\n    cd ..\n    iveriog -o rv32 -Wall *.v\n    vvp -n rv32 # doesn't terminate, press Ctrl+C when it's generated enough output\n\nThe output is in `dump.vcd`, which can be viewed with GTKWave.\n\n## Building the hardware (only required if verilog source is modified)\n\nRequires having built the software at least once to generate the ram initialization files.\n\nRun `(. /opt/Xilinx/14.7/ISE_DS/settings64.sh; ise\u0026)` in a terminal.  \nSwitch the view to Implementation  \nSelect main.v  \nRun \"Generate Programming File\"  \nOpen a terminal and run:\n\n    export PATH=/opt/riscv/bin:\"$PATH\"\n    cd rv32/software\n    make\n    cd ..\n    # at this point the built bitstream is in output.bit\n    djtgcfg prog -d JtagHS2 -i 0 -f output.bit # program the FPGA\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fprogrammerjake%2Frv32","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fprogrammerjake%2Frv32","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fprogrammerjake%2Frv32/lists"}