{"id":23100542,"url":"https://github.com/pseudoincorrect/fpga_mcu_wifi","last_synced_at":"2025-04-03T20:44:54.804Z","repository":{"id":92888936,"uuid":"96317217","full_name":"pseudoincorrect/FPGA_MCU_wifi","owner":"pseudoincorrect","description":"Link between a PC and a FPGA through wifi","archived":false,"fork":false,"pushed_at":"2021-04-13T14:28:14.000Z","size":9084,"stargazers_count":2,"open_issues_count":0,"forks_count":2,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-02-09T09:10:00.686Z","etag":null,"topics":["c","fpga","socket","verilog","wifi"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/pseudoincorrect.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":"Support/FPGA_SOC_Wireless_Transmission_User_Manual.pdf","governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2017-07-05T12:34:26.000Z","updated_at":"2024-05-10T01:12:01.000Z","dependencies_parsed_at":null,"dependency_job_id":"47a231cb-908c-4646-9d39-a8f6936f0c9c","html_url":"https://github.com/pseudoincorrect/FPGA_MCU_wifi","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pseudoincorrect%2FFPGA_MCU_wifi","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pseudoincorrect%2FFPGA_MCU_wifi/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pseudoincorrect%2FFPGA_MCU_wifi/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pseudoincorrect%2FFPGA_MCU_wifi/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/pseudoincorrect","download_url":"https://codeload.github.com/pseudoincorrect/FPGA_MCU_wifi/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247078801,"owners_count":20879950,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["c","fpga","socket","verilog","wifi"],"created_at":"2024-12-16T23:33:02.948Z","updated_at":"2025-04-03T20:44:54.785Z","avatar_url":"https://github.com/pseudoincorrect.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003ch1 align='center'\u003eHybrid FPGA/SOC Wireless Transmission\u003c/h1\u003e\n\n\u003cp align=\"center\"\u003e\u003cimg width=50% src=\"Support/readme_assets/fpgaWifi.jpg\"\u003e\u003c/p\u003e\n\n# Project Overview\n\nThis application is used to transmit data from a FPGA to a PC through WiFi (via a WiFi capable MCU, the CC3200 from TI), up to 8 Mbits/sec.\n\u003cbr\u003e\nA FPGA receive data from several sensors, store them in memory and transmit them to a Microcontroller (MCU) through a SPI connexion. \n\u003cbr\u003e\nThe MCU first connect itself to an Access point (WiFi) and then to a receiving server (in our case a python app). \n\u003cbr\u003e\nAfterward, the MCU start accepting the SPI data sent from the FPGA and store them in a Ring Buffer. \n\u003cbr\u003e\nOnce the ring buffer is full enough, the MCU send data to a computer through the TCP/IP protocol. \n\u003cbr\u003e\nMeanwhile, it still receives data from the SPI. \n\u003cbr\u003e\nThese parallel processes (SPI reception, TCP transmission) repeat endlessly as long as the (socket) connexion between the MCU and the PC stays alive.\n\n\u003cbr\u003e\n\n# Components and Software Used: \n\n- OS\n    - Windows (all tools are available on Linux)\n\n- FPGA\n    - Altera DE2-115\n    - Quartus II 13.1\n\n- SOC\n    - Ti CC3200 launchpad\n    - Code Composer Studio\n\n- Debug\n    - Putty\n    - Logic analyser\n\n- PC Receiver\n    - Linux (netcast)\n    - Pythoneripheral on the chip are used. In our case, 5/6 Mbits per second is a more reasonable throughput. \n\n\u003cbr\u003e\n\n# Repository's folders:\n\n### FPGA/\nContains the verilog code/description for the FPGA transmission\n\n### MCU/\nContains the C code for the CC3200 from TI (wireless app MCU)\n\n### PC_RECEIVER/\nContains the python code to receive data and perform a integrity test on them.\n\u003cbr\u003e\nThis is a terminal/console application.\n\n### Support/\nContains the user manua\n\n\u003cbr\u003e\n\n\n# For more info, please read the user manual\n\u003ca href=\"https://github.com/pseudoincorrect/FPGA_MCU_wifi/support/FPGA_SOC_Wireless_Transmission_User_Manual.pdf\"\u003eMANUAL\u003c/a\u003e","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpseudoincorrect%2Ffpga_mcu_wifi","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpseudoincorrect%2Ffpga_mcu_wifi","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpseudoincorrect%2Ffpga_mcu_wifi/lists"}