{"id":13537074,"url":"https://github.com/pulp-platform/ara","last_synced_at":"2026-02-07T23:36:00.497Z","repository":{"id":38808825,"uuid":"344804156","full_name":"pulp-platform/ara","owner":"pulp-platform","description":"The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 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supports the RISC-V Vector Extension, [version 1.0](https://github.com/riscv/riscv-v-spec/releases/tag/v1.0).\n\nPrototypical documentation can be found at https://pulp-platform.github.io/ara\n\n## Dependencies\n\nCheck `DEPENDENCIES.md` for a list of hardware and software dependencies of Ara.\n\n## Supported instructions\n\nCheck `FUNCTIONALITIES.md` to check which instructions are currently supported by Ara.\n\n## Get started\n\nMake sure you clone this repository recursively to get all the necessary submodules:\n\n```bash\nmake git-submodules\n```\n\nIf the repository path of any submodule changes, run the following command to change your submodule's pointer to the remote repository:\n\n```bash\ngit submodule sync --recursive\n```\n\n## Toolchain\n\nAra requires a RISC-V LLVM toolchain capable of understanding the vector extension, version 1.0.\n\nTo build this toolchain, run the following command in the project's root directory.\n\n```bash\n# Build the LLVM toolchain\nmake toolchain-llvm\n```\n\nAra also requires an updated Spike ISA simulator, with support for the vector extension.\nThere are linking issues with the standard libraries when using newer CC/CXX versions to compile Spike. Therefore, here we resort to older versions of the compilers. If there are problems with dynamic linking, use:\n`make riscv-isa-sim LDFLAGS=\"-static-libstdc++\"`. Spike was compiled successfully using gcc and g++ version 7.2.0.\n\nTo build Spike, run the following command in the project's root directory.\n\n```bash\n# Build Spike\nmake riscv-isa-sim\n```\n\n## Verilator\n\nAra requires an updated version of Verilator, for RTL simulations.\n\nTo build it, run the following command in the project's root directory.\n\n```bash\n# Build Verilator\nmake verilator\n```\n\n## Configuration\n\nAra's parameters are centralized in the `config` folder, which provides several configurations to the vector machine.\nPlease check `config/README.md` for more details.\n\nPrepend `config=chosen_ara_configuration` to your Makefile commands, or export the `ARA_CONFIGURATION` variable to choose a configuration other than the `default` one.\n\n## Software\n\n### Build Applications\n\nThe `apps` folder contains example applications that work on Ara. Run the following command to build an application. E.g., `hello_world`:\n\n```bash\ncd apps\nmake bin/hello_world\n```\n\n### SPIKE Simulation\n\nAll the applications can be simulated with SPIKE. Run the following command to build and run an application. E.g., `hello_world`:\n\n```bash\ncd apps\nmake bin/hello_world.spike\nmake spike-run-hello_world\n```\n\n### RISC-V Tests\n\nThe `apps` folder also contains the RISC-V tests repository, including a few unit tests for the vector instructions. Run the following command to build the unit tests:\n\n```bash\ncd apps\nmake riscv_tests\n```\n\n## RTL Simulation\n\n### Hardware dependencies\n\nThe Ara repository depends on external IPs and uses Bender to handle the IP dependencies.\nTo install Bender and initialize all the hardware IPs, run the following commands:\n\n```bash\n# Go to the hardware folder\ncd hardware\n# Install Bender and checkout all the IPs\nmake checkout\n```\n\n### Patches (only once!)\n\nNote: this step is required only once, and needs to be repeated ONLY if the IP hardware dependencies are deleted and checked out again.\n\nSome of the IPs need to be patched to work with Verilator.\n\n```bash\n# Go to the hardware folder\ncd hardware\n# Apply the patches (only need to run this once)\nmake apply-patches\n```\n\n### Simulation\n\nTo simulate the Ara system with ModelSim, go to the `hardware` folder, which contains all the SystemVerilog files. Use the following command to run your simulation:\n\n```bash\n# Go to the hardware folder\ncd hardware\n# Only compile the hardware without running the simulation.\nmake compile\n# Run the simulation with the *hello_world* binary loaded\napp=hello_world make sim\n# Run the simulation with the *some_binary* binary. This allows specifying the full path to the binary\npreload=/some_path/some_binary make sim\n# Run the simulation without starting the gui\napp=hello_world make simc\n```\n\nWe also provide the `simv` makefile target to run simulations with the Verilator model.\n\n```bash\n# Go to the hardware folder\ncd hardware\n# Apply the patches (only need to run this once)\nmake apply-patches\n# Only compile the hardware without running the simulation.\nmake verilate\n# Run the simulation with the *hello_world* binary loaded\napp=hello_world make simv\n```\n\nIt is also possible to simulate the unit tests compiled in the `apps` folder. Given the number of unit tests, we use Verilator. Use the following command to install Verilator, verilate the design, and run the simulation:\n\n```bash\n# Go to the hardware folder\ncd hardware\n# Apply the patches (only need to run this once)\nmake apply-patches\n# Verilate the design\nmake verilate\n# Run the tests\nmake riscv_tests_simv\n```\n\nAlternatively, you can also use the `riscv_tests` target at Ara's top-level Makefile to both compile the RISC-V tests and run their simulation.\n\n### Traces\n\nAdd `trace=1` to the `verilate`, `simv`, and `riscv_tests_simv` commands to generate waveform traces in the `fst` format.\nYou can use `gtkwave` to open such waveforms.\n\n### Ideal Dispatcher mode\n\nCVA6 can be replaced by an ideal FIFO that dispatches the vector instructions to Ara with the maximum issue-rate possible.\nIn this mode, only Ara and its memory system affect performance.\nThis mode has some limitations:\n - The dispatcher is a simple FIFO. Ara and the dispatcher cannot have complex interactions.\n - Therefore, the vector program should be fire-and-forget. There cannot be runtime dependencies from the vector to the scalar code.\n - Not all the vector instructions are supported, e.g., the ones that use the `rs2` register.\n\nTo compile a program and generate its vector trace:\n\n```bash\ncd apps\nmake bin/${program}.ideal\n```\n\nThis command will generate the `ideal` binary to be loaded in the L2 memory for the simulation (data accessed by the vector code).\nTo run the system in Ideal Dispatcher mode:\n\n```bash\ncd hardware\nmake sim app=${program} ideal_dispatcher=1\n```\n\n### VCD Dumping\n\nIt's possible to dump VCD files for accurate activity-based power analyses. To do so, use the `vcd_dump=1` option to compile the program and to run the simulation:\n\n```bash\nmake -C apps bin/${program} vcd_dump=1\nmake -C hardware simc app=${program} vcd_dump=1\n```\n\nCurrently, the following kernels support automatic VCD dumping: `fmatmul`, `fconv3d`, `fft`, `dwt`, `exp`, `cos`, `log`, `dropout`, `jacobi2d`.\n\n### Linting Flow\n\nWe also provide Synopsys Spyglass linting scripts in the hardware/spyglass. Run make lint in the hardware folder, with a specific MemPool configuration, to run the tests associated with the lint_rtl target.\n\n### Support for `rvv-bench`\n\nTo run `rvv-bench` instructions benchmark, execute:\n\n```bash\nmake rvv-bench\nmake -C apps bin/rvv\nmake -C hardware simv app=rvv\n```\n\n## FPGA implementation and Linux flow\n\nAra supports Cheshire's FPGA flow and can be currently implemented on VCU128 and VCU118 in bare-metal and with Linux. The tested configuration is with 2 lanes.\n\nFor information about the FPGA bare-metal and Linux flows, please refer to `cheshire/README.md`.\n\n## Publications\n\nIf you want to use Ara, you can cite us:\n```\n@Article{Ara2020,\n  author = {Matheus Cavalcante and Fabian Schuiki and Florian Zaruba and Michael Schaffner and Luca Benini},\n  journal= {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},\n  title  = {Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI},\n  year   = {2020},\n  volume = {28},\n  number = {2},\n  pages  = {530-543},\n  doi    = {10.1109/TVLSI.2019.2950087}\n}\n```\n```\n@INPROCEEDINGS{9912071,\n  author={Perotti, Matteo and Cavalcante, Matheus and Wistoff, Nils and Andri, Renzo and Cavigelli, Lukas and Benini, Luca},\n  booktitle={2022 IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)},\n  title={A “New Ara” for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design},\n  year={2022},\n  volume={},\n  number={},\n  pages={43-51},\n  doi={10.1109/ASAP54787.2022.00017}}\n```\n```\n@ARTICLE{10500752,\n  author={Perotti, Matteo and Cavalcante, Matheus and Andri, Renzo and Cavigelli, Lukas and Benini, Luca},\n  journal={IEEE Transactions on Computers},\n  title={Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor},\n  year={2024},\n  volume={73},\n  number={7},\n  pages={1822-1836},\n  keywords={Vectors;Registers;Computer architecture;Vector processors;Multicore processing;Microarchitecture;Kernel;RISC-V;vector;ISA;RVV;processor;efficiency;multi-core},\n  doi={10.1109/TC.2024.3388896}}\n```\n","funding_links":[],"categories":["Accelerators","C","CPUs"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Fara","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpulp-platform%2Fara","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Fara/lists"}