{"id":13995901,"url":"https://github.com/pulp-platform/bigpulp","last_synced_at":"2025-07-22T22:33:00.430Z","repository":{"id":92130261,"uuid":"148470875","full_name":"pulp-platform/bigpulp","owner":"pulp-platform","description":"⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform","archived":true,"fork":false,"pushed_at":"2022-01-06T10:24:44.000Z","size":1936,"stargazers_count":50,"open_issues_count":8,"forks_count":17,"subscribers_count":13,"default_branch":"master","last_synced_at":"2024-08-10T14:21:32.099Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/pulp-platform.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":".github/CODEOWNERS","security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2018-09-12T11:39:55.000Z","updated_at":"2023-08-09T03:31:26.000Z","dependencies_parsed_at":"2024-01-20T18:09:07.711Z","dependency_job_id":"9165a1a2-e555-4835-b310-fb0b1a89aa4e","html_url":"https://github.com/pulp-platform/bigpulp","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fbigpulp","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fbigpulp/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fbigpulp/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fbigpulp/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/pulp-platform","download_url":"https://codeload.github.com/pulp-platform/bigpulp/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":227190485,"owners_count":17745272,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-09T14:03:39.099Z","updated_at":"2024-11-29T18:31:18.883Z","avatar_url":"https://github.com/pulp-platform.png","language":"SystemVerilog","funding_links":[],"categories":["Open Source Implementations","SystemVerilog"],"sub_categories":["Cores"],"readme":"# DEPRECATED\n\nThis repository is part of a deprecated version of HERO.  Please refer to the [current HERO repository](https://github.com/pulp-platform/hero) for the current accelerator hardware.\n\n# bigPULP\n\n![HERO hardware overview with bigPULP implemented on FPGA](doc/hero_hw_overview.png)\n\nHERO is our open-source, FPGA-based, heterogeneous embedded SoC research\nplatform that combines a fully-modifiable RISC-V manycore accelerator with\nan ARM Cortex-A host processor.\n\nHERO consists of many different hard- and software components. This repository\ncontains the bigPULP hardware platform, i.e., the sources and build scripts to\ngenerate the FPGA bitstream implementing the RISC-V manycore accelerator of HERO.\n\nBeing the big brother of the open-source, multicore, Parallel Ultra-Low Power\n(PULP) computing platform jointly developed by ETH Zurich and the\nUniversity of Bologna, bigPULP is based on the same cluster architecture and\nsources. Depending on the target FPGA, bigPULP uses one or multiple PULP clusters\nthat share an L2 instruction and data memory, a global interconnect,\nsynchronization infrastructure, as well as the Remap Address Block (RAB) - a\nsoftware-managed I/O memory management unit - which allows accelerator to\ncoherently access the platform's main memory including support for shared virtual\nmemory (SVM).\n\nFor further information about HERO, refer to our HERO paper at\nhttps://arxiv.org/abs/1712.06497 and the HERO website https://www.pulp-platform.org/hero/.\n\nDetailed HOWTOs on how to build and use the HERO platform can be found here:\n\n\u003cp align=\"center\"\u003ehttps://pulp-platform.org/hero/doc/\u003c/p\u003e\n\n\nFor more information about the PULP project in general, please refer to the official PULP platform website:\n\n\u003cp align=\"center\"\u003ehttps://www.pulp-platform.org/\u003c/p\u003e\n\n\n## Getting Started\n\n### Preparation\nBefore being able to build a bitstream or simulate the FPGA design, get the\nlatest version of the IP cores used inside bigPULP:\n```\n./update-ips\n```\nThis will download all the required IPs, solve dependencies and generate the\nscripts by calling `./generate-scripts`.\n\nThen, enter the `fpga` directory and adjust the `sourceme.sh` script. Select\nthe target board and adjust the path to the Vivado-specific simulation libraries.\n\nSource the `sourceme.sh` script:\n```\n. sourceme.sh\n```\n\nGenerate all the Xilinx IP cores used inside bigPULP:\n```\nmake ips\n```\n\n### Generating the FPGA bitstream\nAfter having downloaded the PULP IP cores, having set up and sourced the\n`sourceme.sh` script and having generated the Xilinx IP cores as shown in the\npreparation section, you can start generating an FPGA bitstream. To this end,\nenter the `fpga` directory and execute\n```\nmake synth-pulp_cluster\n```\nto start Xilinx Vivado and synthesize the cluster netlist. Afterwards, run\n```\nmake synth-pulp_soc\n```\nto start Xilinx Vivado and synthesize the SoC containing possibly multiple\nclusters as well as SoC-level IP cores.\n\nFinally, the top-level design containing the bigPULP SoC and the interfaces\nto the host can be generated and an FPGA bitstream can be generated. To this\nend, enter the folder `bigpulp-z-70xx` and run\n```\nmake clean gui\n```\nto start Xilinx Vivado, synthesize the top-level netlist and generate the\nFPGA bitstream.\n\n**NOTE**: When targeting other platforms such as the Xilinx Zynq UltraScale+ MPSoC\nor the Juno ARM Development Platform, enter the corresponding directory, i.e.,\n`bigpulp-zux` or `bigpulp`, respectively.\n\nHow to create a bootable HERO system image using the generated FPGA bitstream is\nis shown in a detailed HOWTO at:\nhttps://pulp-platform.org/hero/doc/software\n\n### Simulating the FPGA design\nTo debug the bigPULP platform, this repository provides a set of simulation\nscripts and testbenches.\n\n**NOTE**: The simulation platform only models the bigPULP subsystem. The host is\nnot part of the simulation. Instead, the host is modeled using an AXI master plug\ndriven by the testbench, and the shared main memory is modeled using Xilinx BRAM\nIP cores.\n\nAfter having downloaded the PULP IP cores, having set up the `sourceme.sh` script\nand having generated the Xilinx IP cores as shown in the preparation section, you\nneed to download the free AMBA4 AXI-Lite Verification IP from SysWip:\nhttp://syswip.com/axi4-lite-verification-ip\nand extract the archive.\n\nThen, open the `sourceme.sh` script and adjust the `AXI4LITE_VIP_PATH` variable\nto point to where you just extracted the archive.\n\nSource the `sourceme.sh` script:\n```\n. sourceme.sh\n```\n\nNext, copy the `.slm` files, i.e., memory initialization files for the application\nof interest, to the folder `sim-bigpulp-z-70xx/tb/current/slm_files`. These files\nare generated by the PULP SDK when compiling an application. They are typically found\ninside the build directory `build/system-bigpulp*/`.\n\nFinally, enter the folder `sim-bigpulp-z-70xx/vivado` and run\n```\nmake clean gui\n```\nto start Xilinx Vivado, compile the entire design and start the RTL simulation.\n\n**NOTE**: When targeting other platforms such as the Xilinx Zynq UltraScale+ MPSoC\nor the Juno ARM Development Platform, enter the corresponding directory, i.e.,\n`sim-bigpulp-zux/vivado` or `sim-bigpulp/vivado`, respectively.\n\n## bigPULP repository structure\nAfter being fully setup as explained in the Getting Started section, this root\nrepository is structured as follows:\n- `fe` contains the front-end RTL code of bigPULP.\n- `fe/rtl` contains the main platform RTL code including packages a\n  include files.\n- `fe/ips` contains all IPs downloaded by `update-ips` script.\n- `fpga` contains all FPGA-specific files to build and simulate the RTL code\n  including:\n  - `fpga/rtl`: FPGA-specific RTL code.\n  - `fpga/ips`: Vivado build scripts to generate the Xilinx IP cores instantiated\n    in the design.\n  - `fpga/pulp_cluster`: Vivado build scripts to generate the netlist of the\n    PULP cluster IP instantiated in the design.\n  - `fpga/pulp_soc`: Vivado build scripts to generate the netlist of the bigPULP\n    SoC containing one or multiple PULP clusters as well as SoC-level IPs such as\n    the RAB.\n  - `fpga/bigpulp-z-70xx`: Vivado build scripts and top-level RTL files to\n    generate the bigPULP bitstream and Xilinx SDK files for HERO based on\n    Xilinx Zynq-7000 SoCs.\n  - `fpga/sim-bigpulp-z-70xx`: Vivado scripts and testbenches to simulate\n    bigPULP when targeting Xilinx Zynq-7000 SoCs.\n  - `fpga/bigpulp-zux`: Vivado build scripts and top-level RTL files to\n     generate the bigPULP bitstream, Xilinx SDK and PetaLinux input files\n     for HERO based on Xilinx Zynq UltraScale+ MPSoCs.\n  - `fpga/sim-bigpulp-zux`: Vivado scripts and testbenches to simulate bigPULP\n    when targeting Xilinx Zynq UltraScale+ MPSoCs.\n  - `fpga/bigpulp`: Vivado build scripts and support files to generate the\n    multicluster bigPULP bitstream for HERO based on the\n    ARM Juno Development Platform.\n  - `fpga/sim-bigpulp`: Vivado scripts and testbenches to simulate bigPULP when\n    targeting the ARM Juno Development Platform.\n\n- `ipstools` contains the utilities to download and manage the IPs and their\n  dependencies.\n- `ips_list.yml` contains the list of IPs required directly by the platform.\n  Notice that each of them could in turn depend on other IPs, so you will\n  typically find many more IPs in the `ips` directory than are listed in\n  this file.\n- `rtl_list.yml` contains the list of places where local RTL sources are found\n  (e.g. `fe/rtl/components`).\n\n## Requirements\nThe RTL platform has the following requirements:\n- Relatively recent Linux-based operating system; we tested *Ubuntu 16.04* and\n  *CentOS 7*.\n- Xilinx Vivado Design Suite version *2017.2*.\n- ModelSim in reasonably recent version (we tested it with version *10.6b*).\n- Python 3.4, with the `pyyaml` module installed (you can get that with\n  `pip3 install pyyaml`).\n\n## Repository organization\nThe PULP platforms are highly hierarchical and the Git repositories for the various\nIPs follow the hierarchy structure to keep maximum flexibility.\nMost of the complexity of the IP updating system are hidden behind the\n`update-ips` and `generate-scripts` Python scripts; however, a few details are\nimportant to know:\n- Do not assume that the `master` branch of an arbitrary IP is stable; many\n  internal IPs could include unstable changes at a certain point of their\n  history. Conversely, in top-level platforms (`pulpissimo`, `pulp`, `bigPULP`)\n  we always use *stable* versions of the IPs. Therefore, you should be able to use\n  the `master` branch of `bigPULP` safely.\n- By default, the IPs will be collected from GitHub using HTTPS. This makes it\n  possible for everyone to clone them without first uploading an SSH key to\n  GitHub. However, for development it is often easier to use SSH instead,\n  particularly if you want to push changes back.\n  To enable this, just replace `https://github.com` with `git@github.com` in the\n  `ipstools_cfg.py` configuration file in the root of this repository.\n\nThe tools used to collect IPs and create scripts for simulation have many\nfeatures that are not necessarily intended for the end user, but can be useful\nfor developers; if you want more information, e.g. to integrate your own\nrepository into the flow, you can find documentation at\nhttps://github.com/pulp-platform/IPApproX/blob/master/README.md\n\n## External contributions\nThe supported way to provide external contributions is by forking one of our\nrepositories, applying your patch and submitting a pull request where you\ndescribe your changes in detail, along with motivations.\nThe pull request will be evaluated and checked with our regression test suite\nfor possible integration.\nIf you want to replace our version of an IP with your GitHub fork, just add\n`group: YOUR_GITHUB_NAMESPACE` to its entry in `ips_list.yml` or\n`ips/pulp_soc/ips_list.yml`.\nWhile we are quite relaxed in terms of coding style, please try to follow these\nrecommendations:\nhttps://github.com/pulp-platform/ariane/blob/master/CONTRIBUTING.md\n\n## Known issues\nCurrently, the bigPULP platform cannot be built for the Juno ARM Development\nPlatform from the sources in this repository since part of the required IP cores\nand top-level wrappers from ARM are not freely available. For internal development,\ndownload the `juno-support` repository from the internal GitLab server and\nconfigure `JUNO_SUPPORT_PATH` in `sourceme.sh` accordingly.\n\n## Support \u0026 Questions\nFor support on any issue related to this platform or any of the IPs, please add\nan issue to our tracker on https://github.com/pulp-platform/bigPULP/issues\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Fbigpulp","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpulp-platform%2Fbigpulp","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Fbigpulp/lists"}