{"id":44052305,"url":"https://github.com/pulp-platform/clic","last_synced_at":"2026-02-07T23:36:00.885Z","repository":{"id":43169761,"uuid":"453448013","full_name":"pulp-platform/clic","owner":"pulp-platform","description":"RISC-V fast interrupt controller","archived":false,"fork":false,"pushed_at":"2025-09-30T09:43:53.000Z","size":257,"stargazers_count":29,"open_issues_count":10,"forks_count":4,"subscribers_count":5,"default_branch":"master","last_synced_at":"2025-09-30T11:36:49.247Z","etag":null,"topics":["clic","interrupt","risc-v"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/pulp-platform.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2022-01-29T16:11:53.000Z","updated_at":"2025-09-30T09:41:52.000Z","dependencies_parsed_at":"2023-09-26T11:49:55.390Z","dependency_job_id":"69d13eac-7de8-4e4a-9454-3ce7334c79b9","html_url":"https://github.com/pulp-platform/clic","commit_stats":null,"previous_names":[],"tags_count":11,"template":false,"template_full_name":null,"purl":"pkg:github/pulp-platform/clic","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fclic","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fclic/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fclic/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fclic/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/pulp-platform","download_url":"https://codeload.github.com/pulp-platform/clic/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fclic/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29212754,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-07T23:14:30.912Z","status":"ssl_error","status_checked_at":"2026-02-07T23:14:17.253Z","response_time":63,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["clic","interrupt","risc-v"],"created_at":"2026-02-07T23:36:00.356Z","updated_at":"2026-02-07T23:36:00.875Z","avatar_url":"https://github.com/pulp-platform.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RISC-V CLIC\nRISC-V Core Local Interrupt Controller (CLIC) is an interrupt controller for\nRISC-V cores subsuming the original RISC-V local interrupt scheme (CLINT). It\npromises pre-emptive, low-latency, vectored, priority/level based interrupts.\n\nThis IP is meant to be used together with a suitably modified version of a core.\nCurrently, a modified version of the\n[CV32E40P](https://github.com/openhwgroup/cv32e40p) is supported.\n\n[Here](./doc/clic.adoc) is the detailed specification this IP is based on. For\nthe upstream specification visit\n[this](https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc)\nlink.\n\nNote that this IP is based on an intermediate development version of the CLIC\nspecification which will still change substantially. This IP will try to track\nthe changes of the specification. The [specification document](./doc/clic.adoc)\nin this repository is a snapshot of the upstream specification and the version\nthis IP is based on.\n\n## Features\n\n- RISC-V Core Local Interrupt Controller (CLIC) compliant interrupt controller\n- Support up to 4096 interrupt lines\n- Support up to 8 bits of priority/level information per interrupt line\n- Supports (a modified) [CV32E40P](#CLIC-and-CV32E40P)\n\n## Parametrization\nSome parameters are configurable. See the marked variables in the table below.\n\n```\nName             Value Range                   Description\nCLICANDBASIC     0-1     (depends on core)     Implements original basic mode also?\nCLICPRIVMODES    1-3     (depends on core)     Number privilege modes: 1=M, 2=M/U,\n                                                                       3=M/S/U\nCLICLEVELS       2-256                         Number of interrupt levels including 0\n*NUM_INTERRUPT*  4-4096  (default=256)         Always has MSIP, MTIP, MEIP, CSIP\nCLICMAXID        12-4095                       Largest interrupt ID\n*CLICINTCTLBITS* 0-8     (default=8)           Number of bits implemented in\n                                               clicintctl[i]\nCLICCFGMBITS     0-ceil(lg2(CLICPRIVMODES))    Number of bits implemented for\n                                               cliccfg.nmbits\nCLICCFGLBITS     0-ceil(lg2(CLICLEVELS))       Number of bits implemented for\n                                               cliccfg.nlbits\nCLICSELHVEC      0-1     (0-1)                 Selective hardware vectoring supported?\nCLICMTVECALIGN   6-13    (depends on core)     Number of hardwired-zero least\n                                               significant bits in mtvec address.\nCLICXNXTI        0-1     (depends on core)     Has xnxti CSR implemented?\nCLICXCSW         0-1     (depends on core)     Has xscratchcsw/xscratchcswl\n                                               implemented?\n```\n\n## Integration and Dependencies\nThis IP requires\n\n- [common_cells](https://github.com/pulp-platform/common_cells)\n- [register_interface](https://github.com/pulp-platform/register_interface)\n\nand a suitably modified core (see sections below).\n\nThe [bender](https://github.com/pulp-platform/bender) and legacy\n[IPApproX](https://github.com/pulp-platform/IPApproX) flow are supported.\n\nBesides the native\n[register_interface](https://github.com/pulp-platform/register_interface) there\nis an APB wrapper available.\n\n\n## CLIC and CV32E40P\nThe patch required to use the CV32E40P together with the CLIC lives in this\n[branch](https://github.com/pulp-platform/cv32e40p/tree/clic). The CLIC mode is\nan elaboration time parameter at this moment, but will support a dynamic switch\nat some point.\n\nHere is the summary\n```\nName             Value\nCLICANDBASIC     0   (dynamic mode under development)\nCLICPRIVMODES    2\nNUM_INTERRUPT    32-256\nCLICINTCTLBITS   0-8\nCLICSELHVEC      1\nCLICMTVECALIGN   8\nCLICXNXTI        0   (partial, under development)\nCLICXCSW         1\n```\n\n## CLIC and CVA6\nNot supported yet.\n\n## FreeRTOS Support\nThere is very basic support for the CLIC in\n[pulp-freertos](https://github.com/pulp-platform/pulp-freertos) with more a more\ncomplete level/priority implementation in the works.\n\n## Register interface\nBy default the CLIC's register file is manually written requiring no attention\nof the user.\n\nAlternatively, [regtool](https://docs.opentitan.org/doc/rm/register_tool/) can\nbe used to generate the register file. For that, go to `src/gen/` and call `make\nall` with the environment variable `REGTOOL` pointing to `regtool.py` of the\n[register_interface](https://github.com/pulp-platform/register_interface)\nrepository and `NUM_INTERRUPT` and `CLICINTCTLBITS` appropriately set. These\nthree environment variables can be passed when using make, e.g. \n\n```console\n    make NUM_INTERRUPT=128 CLICINTCTLBITS=4\n```\n\nFinally, make sure your `src_files.yml` or `Bender.yml` points to\n\n- `src/gen/clic_reg_pkg.sv`\n- `src/gen/clic_reg_top.sv`\n- `src/gen/clic_reg_adapater.sv`\n\n`regtool` has various limitations on how the register map can look like,\nrequiring the memory map description (`src/gen/clic.hjson`) to be derived from a\ntemplate (`src/gen/clic.hjson.tpl`), resulting in rather unwieldy code and\ndocumentation.\n\n## Directory Structure\n```\n.\n├── doc      CLIC spec, Blockdiagrams\n├── src      RTL\n├── src/gen  Templates and python scripts\n```\n\n## License\nThis project uses sourcecode from lowRISC licensed under Apache 2.0. The changes\nand additions are being made available using Apache 2.0 see LICENSE for more\ndetails.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Fclic","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpulp-platform%2Fclic","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Fclic/lists"}