{"id":13537490,"url":"https://github.com/pulp-platform/pulpissimo","last_synced_at":"2026-02-07T23:36:22.378Z","repository":{"id":29265672,"uuid":"120891675","full_name":"pulp-platform/pulpissimo","owner":"pulp-platform","description":"This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.","archived":false,"fork":false,"pushed_at":"2025-05-15T19:27:34.000Z","size":9524,"stargazers_count":446,"open_issues_count":132,"forks_count":186,"subscribers_count":40,"default_branch":"master","last_synced_at":"2025-10-31T21:51:28.684Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/pulp-platform.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":null,"funding":null,"license":"LICENSE.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-02-09T10:24:02.000Z","updated_at":"2025-10-22T07:15:30.000Z","dependencies_parsed_at":"2024-02-26T10:49:37.320Z","dependency_job_id":"c20386f7-9621-42bd-a0cd-0605cfced1ad","html_url":"https://github.com/pulp-platform/pulpissimo","commit_stats":null,"previous_names":[],"tags_count":10,"template":false,"template_full_name":null,"purl":"pkg:github/pulp-platform/pulpissimo","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fpulpissimo","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fpulpissimo/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fpulpissimo/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fpulpissimo/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/pulp-platform","download_url":"https://codeload.github.com/pulp-platform/pulpissimo/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fpulpissimo/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29212755,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-07T23:36:15.537Z","status":"ssl_error","status_checked_at":"2026-02-07T23:36:12.879Z","response_time":63,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T09:00:59.585Z","updated_at":"2026-02-07T23:36:17.370Z","avatar_url":"https://github.com/pulp-platform.png","language":"SystemVerilog","funding_links":[],"categories":["Systems","SystemVerilog","Open Source Toolchains"],"sub_categories":["Design Environment"],"readme":"# PULPissimo\n\n## Citing\nIf you are using the PULPissimo IPs for an academic publication, please cite the following paper:\n\n```\n@INPROCEEDINGS{8640145,\n  author={Schiavone, Pasquale Davide and Rossi, Davide and Pullini, Antonio and Di Mauro, Alfio and Conti, Francesco and Benini, Luca},\n  booktitle={2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)}, \n  title={Quentin: an Ultra-Low-Power PULPissimo SoC in 22nm FDX}, \n  year={2018},\n  volume={},\n  number={},\n  pages={1-3},\n  doi={10.1109/S3S.2018.8640145}}\n```\n\n![](doc/pulpissimo_archi.png)\n\nPULPissimo is the microcontroller architecture of the more recent PULP chips,\npart of the ongoing \"PULP platform\" collaboration between ETH Zurich and the\nUniversity of Bologna - started in 2013.\n\nPULPissimo, like PULPino, is a single-core platform. However, it represents a\nsignificant step ahead in terms of completeness and complexity with respect to\nPULPino - in fact, the PULPissimo system is used as the main System-on-Chip\ncontroller for all recent multi-core PULP chips, taking care of autonomous I/O,\nadvanced data pre-processing, external interrupts, etc.\nThe PULPissimo architecture includes:\n\n- Either the RI5CY core or the Ibex one as main core\n- Autonomous Input/Output subsystem (uDMA)\n- New memory subsystem\n- Support for Hardware Processing Engines (HWPEs)\n- New simple interrupt controller\n- New peripherals\n- New SDK\n\nRISCY is an in-order, single-issue core with 4 pipeline stages and it has\nan IPC close to 1, full support for the base integer instruction set (RV32I),\ncompressed instructions (RV32C) and multiplication instruction set extension\n(RV32M). It can be configured to have single-precision floating-point\ninstruction set extension (RV32F). It implements several ISA extensions\nsuch as: hardware loops, post-incrementing load and store instructions,\nbit-manipulation instructions, MAC operations, support fixed-point operations,\npacked-SIMD instructions and the dot product. It has been designed to increase\nthe energy efficiency of in ultra-low-power signal processing applications.\nRISCY implementes a subset of the 1.10 privileged specification.\nIt includes an optional PMP and the possibility to have a subset of the USER MODE.\nRISCY implement the RISC-V Debug spec 0.13.\nFurther information about the core can be found at\nhttp://ieeexplore.ieee.org/abstract/document/7864441/\nand in the documentation of the IP.\n\nIbex, formely Zero-riscy, is an in-order, single-issue core with 2 pipeline\nstages. It has full support for the base integer instruction set (RV32I\nversion 2.1) and compressed instructions (RV32C version 2.0).\nIt can be configured to support the multiplication instruction set extension\n(RV32M version 2.0) and the reduced number of registers extension (RV32E\nversion 1.9). Ibex implementes the Machine ISA version 1.11 and has RISC-V\nExternal Debug Support version 0.13.2. Ibex has been originally designed at\nETH to target ultra-low-power and ultra-low-area constraints. Ibex is now\nmaintained and further developed by the non-for-profit community interest\ncompany lowRISC. Further information about the core can be found at\nhttp://ieeexplore.ieee.org/document/8106976/\nand in the documentation of the IP at\nhttps://ibex-core.readthedocs.io/en/latest/index.html\n\nPULPissimo includes a new efficient I/O subsystem via a uDMA (micro-DMA) which\ncommunicates with the peripherals autonomously. The core just needs to program\nthe uDMA and wait for it to handle the transfer.\nFurther information about the core can be found at\nhttp://ieeexplore.ieee.org/document/8106971/\nand in the documentation of the IP.\n\nPULPissimo supports I/O on interfaces such as:\n\n- SPI (as master)\n- I2S\n- Camera Interface (CPI)\n- I2C\n- UART\n- Hyperbus\n- JTAG\n\nPULPissimo also supports integration of hardware accelerators (Hardware\nProcessing Engines) that share memory with the RI5CY core and are programmed on\nthe memory map. An example accelerator, performing multiply-accumulate on a\nvector of fixed-point values, can be found in `ips/hwpe-mac-engine` (after\nupdating the IPs: see below in the Getting Started section).\nThe `ips/hwpe-stream` and `ips/hwpe-ctrl` folders contain the IPs necessary to\nplug streaming accelerators into a PULPissimo or PULP system on the data and\ncontrol plane.\nFor further information on how to design and integrate such accelerators,\nsee `ips/hwpe-stream/doc` and https://arxiv.org/abs/1612.05974.\n\n## Documentation\n\n- The [datasheet](doc/datasheet/datasheet.pdf) contains details about Memory Map, Peripherals, Registers etc. This may not be fully up-to-date.\n- PULPissimo was presented at the Week of Open Source Hardware (WOSH) 2019 at ETH Zurich.\n  - [Slides](https://pulp-platform.org/docs/riscv_workshop_zurich/schiavone_wosh2019_tutorial.pdf)\n  - [Video](https://www.youtube.com/watch?v=27tndT6cBH0)\n\n## Getting Started\nWe provide a [simple runtime](#simple-runtime) and a [full featured\nruntime](#software-development-kit) for PULPissimo. We recommend you try out\nfirst the minimal runtime and when you hit its limitations you can try the full\nruntime by installing the SDK.\n\nAfter having chosen a runtime you can run software by either [simulating the\nhardware](#building-the-rtl-simulation-platform) or running it in a [software\nemulation](#building-and-using-the-virtual-platform).\n\n### Prerequisites\nPULPissimo is a Microcontroller provided in SystemVerilog RTL description. As such,\nit can be used and evaluated with many different tools. Out of the box, we provide Makefile\ntargets for RTL simulation with Mentor Questa SIM (Intel/Altera Modelsim is not supported at the moment)\nand Cadence Xcelium. Being purely written in SystemVerilog, in theory the whole design can be simulated \nwith any RTL simulator with (deccent!) SystemVerilog support. While an open source simulation target is \ndefinitely on our wish- and todo-list (e.g. out-of-the box support for Verilator), this currently\nstill requires more extensive modifications to the RTL and scripts.\n\nFor FPGA implementation (see [FPGA Section](#FPGA)) we generate ready-made scripts for Synthesis and Implementation \nfor Xilinx Vivado for a number of different development boards.\n\n### Simple Runtime\nThe simple runtime is here to get you started quickly. Using it can run and\nwrite programs that don't need any advanced features.\n\nFirst install the system dependencies indicated\n[here](https://github.com/pulp-platform/pulp-runtime/blob/master/README.md)\n\nThen make sure you have\n[riscv-gnu-toolchain](https://github.com/pulp-platform/riscv-gnu-toolchain)\ninstalled (either by compiling it or using one of the binary releases under\navailable under the release tab) and point `PULP_RISCV_GCC_TOOLCHAIN` to it:\n\n```\nexport PULP_RISCV_GCC_TOOLCHAIN=YOUR_PULP_TOOLCHAIN_PATH\n```\nAdd the pulp-toolchain to your PATH variable:\n\n```\nexport PATH=$PULP_RISCV_GCC_TOOLCHAIN/bin:$PATH\n```\n\n\nThe repository for the simple runtime is included as a submodule:\n```\ngit submodule update --init --recursive\n```\nThe simple runtime supports many different hardware configurations. We want PULPissimo.\n\n```\ncd sw/pulp-runtime\n```\nThen, to use the CV32E40P (formely RI5CY) core, type:\n\n```\nsource configs/pulpissimo_cv32.sh\n```\n\nor to use the Ibex (formely zero-riscy) core:\n\n```\nsource configs/pulpissimo_ibex.sh\n```\n\n\nNow we are ready to set up the simulation environment. Normally you would want\nto simulate the hardware design running your program, so go\n[here](#building-the-rtl-simulation-platform).\n\n### PULP FreeRTOS\nPULP FreeRTOS allows you to build applications using the FreeRTOS kernel. You\ncan also choose to not use the FreeRTOS kernel and build a baremetal\napplication, though in that case driver support is not yet fully fleshed out.\n\nFirst make sure you have\n[riscv-gnu-toolchain](https://github.com/pulp-platform/riscv-gnu-toolchain)\ninstalled (either by compiling it or using one of the binary releases under\navailable under the release tab) and point your `RISCV` environment variable to\nit.\n\nAlso we need to set up the simulation environment. Normally you would want to\nsimulate the hardware design running your program, so go\n[here](#building-the-rtl-simulation-platform) to do that.\n\n\nThen get the repository for the pulp-freertos:\n```\ngit clone https://github.com/pulp-platform/pulp-freertos/ sw/pulp-freertos\n```\n\nThere are multiple hardware configuration supported. Select PULPissimo using the\nCV32E40P core.\nSo enter the directory of pulp-freertos:\n\n```\ncd sw/pulp-freertos\n```\n\nand select the correct configuration:\n\n```\nsource env/pulpissimo-cv32e40p.sh\n```\n\nYou then can run a simple freertos hello world like this:\n\n```\ncd tests/hello_world_pmsis\nmake all run\n```\n\nThere are other tests in `tests/` you can run.\n\n### ~~Software Development Kit~~ (UNSUPPORTED WITH CURRENT RELEASE)\n\nIf you need a more complete runtime (drivers, tasks etc.) you can install the\nsoftware development kit for PULP/PULPissimo.\n\nFirst install the system dependencies indicated\n[here](https://github.com/pulp-platform/pulp-builder/blob/master/README.md)\n\nIn particular don't forget to set `PULP_RISCV_GCC_TOOLCHAIN`.\n\nYou can now either follow the steps outlined [here](https://github.com/pulp-platform/pulp-sdk/#standard-sdk-build)\nto build the full sdk or install these python dependencies\n```\npip3 install --user artifactory twisted prettytable sqlalchemy pyelftools 'openpyxl==2.6.4' xlsxwriter pyyaml numpy configparser pyvcd sphinx\n```\nand just call\n```\nmake build-pulp-sdk\n```\nand then set up the necessary environment variables with\n```\nsource env/pulpissimo.sh\n```\n\nThere exists a bug in GCC 11.1.0 which fails the sdk build with the error `'this' pointer is null [-Werror=nonnull]`.\nIf you encounter this bug use the following temporary workaround instead to build the SDK:\n\n```\nVP_WORKAROUND_NONNULL_BUG=yes make build-pulp-sdk\n```\n\n### Building the RTL simulation platform\nNote you need Questasim or Xcelium to do an RTL simulation of PULPissimo\n(verilator support planned, but not finished). Intel Modelsim for Intel FPGAs\ndoes *not* work.\n\nTo build the RTL simulation platform, start by getting the latest version of the\nIPs composing the PULP system:\n```bash\nmake checkout\n```\n\nThis will download all the required IPs, solve dependencies and generate the\nscripts. The dependency management tool is\n[Bender](https://github.com/pulp-platform/bender).\n\nAfter having access to the SDK, you can build the simulation platform by doing\nthe following:\n```bash\nmake build\n```\nThis command builds a version of the simulation platform with no dependencies on\nexternal models for peripherals. See below (Proprietary verification IPs) for\ndetails on how to plug in some models of real SPI, I2C, I2S peripherals.\n\nFor more advanced usage have a look at `./utils/bin/bender --help` for bender.\n\n\nAlso check out the output of `make help` for more useful Makefile targets.\n\n### Developing your own RTL\n#### Bender How To\nWith Bender developing on top of PULPissimo is getting a lot easier. The command\nline tool is installed in the project root directory if you invoke `make\ncheckout`. It performs dependency resolution according to a manifest\nfile called `Bender.yml`. The file lists all source files of the RTL project as\nwell as its direct dependencies. Bender can be used to generate source file\nlists for various different tools for simulation, ASIC/FPGA synthesis etc. Have\na look at the Bender [project\ndocumentation](https://github.com/pulp-platform/bender) if you want to know more\nabout it. For now we will concentrate on the most important steps when\ndeveloping on PULPissimo using Bender.\n\n#### Where are all the sub IPs (dependencies)?\nBender checks out the sub-ips in a hidden directory called\n`.bender/git/checkouts`. **You are not supposed to change the files in this\ndirectory.** If you want to get the path of a specific IP, call `./bender path\n\u003csome ip (e.g. axi)\u003e` to get the relative path to an IP. To list all IPs in the\nproject, call `./bender packages -f`.\n\n#### Modifying an existing IP\nThe hidden bender directory is not the location to introduce changes to the RTL\nof sub-ips. If you want to quickly try out changes to a sub-ip, call `./bender\nclone \u003cip_name\u003e` to checkout a working copy of the ip into a directory called\n`working_dir`. Call `make scripts` to update the source files in the scripts.\nAfterwards, every change you make in the RTL of this working copy will be\nincorporated into the RTL simulation model (once you recompile it with\n`make build`) and the FPGA build (once you synthesize it).\n\n#### Adding a new IP to PULPissimo\nIf you want to add new IPs to pulpissimo you most likely will have to fork the\n`pulp_soc` sub-ip since this is the main repository that contains most of the\nSoCs RTL logic. Thus, follow the steps above to create a working copy of\npulp_soc. Then you can either add your additional source code directly to\n`pulp_soc`s source tree or, preferably, create a new repository with your source\ncode, register the RTL source files in a `Bender.yml` manifest file and add this\nnew repository as a dependency to `pulp_soc`'s `Bender.yml`. Then you are free\nto instantiate your new IP somewhere within pulp_soc. We make excessive use of\nthis strategy throughout the pulpissimo project which is a collection of many\ndifferent IP repositories.\n\n\n### Downloading and running examples\nFinally, you can download and run examples; for that you can checkout the following repositories depending on whether you use the simple runtime or the full sdk.\n\nSimple Runtime: https://github.com/pulp-platform/pulp-runtime-examples\n\nSDK: https://github.com/pulp-platform/pulp-rt-examples\n\nNow you can change directory to your favourite test e.g.: for an hello world\ntest for the SDK, run\n```bash\ncd pulp-rt-examples/hello\nmake clean all run\n```\nor for the Simple Runtime:\n\n```bash\ncd pulp-runtime-examples/hello\nmake clean all run\n```\n\nIf you want to change the compiler flags, as for example \nif you are using CV32E40P with the XPULP extensions but you want to compile \nusing only the RV32IMC instructions to compare performance,\nyou can modify the Makefile inside the pulp-runtime-examples/hello folder adding:\n\n```\nPULP_ARCH_CFLAGS    =  -march=rv32imc -DRV_ISA_RV32\nPULP_ARCH_LDFLAGS   =  -march=rv32imc\nPULP_ARCH_OBJDFLAGS = -Mmarch=rv32imc\n```\nThe open-source simulation platform relies on JTAG to emulate preloading of the\nPULP L2 memory. If you want to simulate a more realistic scenario (e.g.\naccessing an external SPI Flash), look at the sections below.\n\nIn case you want to see the Modelsim GUI, just type\n```bash\nmake run gui=1\n```\nbefore starting the simulation.\n\nIf you want to save a (compressed) VCD for further examination, type\n```bash\nmake run vsim/script=export_run.tcl\n```\nbefore starting the simulation. You will find the VCD in\n`build/\u003cSRC_FILE_NAME\u003e/pulpissimo/export.vcd.gz` where\n`\u003cSRC_FILE_NAME\u003e` is the name of the C source of the test.\n\n### Building and using the virtual platform\nThe virtual platform is a software-only model of the PULPissimo SoC (and also of\nother related SoCs). While a simulation of the hardware design is accurate it is\nalso very very slow. The virtual platform helps you develop software quicker by\nproviding a more or less accurate software-model of PULPissimo.\n\nOnce the sdk is installed, the following commands can be executed in the sdk\ndirectory to use the virtual platform:\n```bash\nsource sourceme.sh\nsource configs/platform-gvsoc.sh\n```\n\nThen tests can be compiled and run as for the RTL platform. When switching from\none platform to another, it may be needed to regenrate the test configuration\nwith this command:\n```bash\nmake conf\n```\n\nMore information is available in the documentation here: pulp-builder/install/doc/vp/index.html\n\n### Updating the bootrom\nYou can customize the bootrom, have a look at the `sw/bootcode/` directory. To\nimport your changed version of the boot code into PULPissimo, just call\n```\nmake bootrom\n```\n\n## FPGA\n\nPULPissimo has been implemented on FPGA for the various Xilinx FPGA boards.\n\n### Supported Boards\nAt the moment the following boards are supported:\n* Digilent Genesys2\n* Xilinx ZCU104\n* Xilinx ZCU102\n* Xilinx VCU108\n* Digilent Nexys Board Family\n* ZedBoard\n\nIn the release section you find precompiled bitstreams for all of the above\nmentionied boards. If you want to use the latest development version PULPissimo\nfollow the section below to generate the bitstreams yourself.\n\n### Bitstream Generation\nIn order to generate the PULPissimo bitstream for a supported target FPGA board\nyou can directly generate the bitstream for the desired board by running the\ncorresponding make target.\n\nThis will parse the `Bender.yml` using the PULP bender dependency management tool to\ngenerate tcl scripts for all the IPs used in the PULPissimo project. These files\nare later on sourced by Vivado to generate the bitstream for PULPissimo.\n\nYou can also switch to the fpga subdirectory and start the apropriate make target to\ngenerate the bitstream:\n\n```Shell\ncd target/fpga\nmake \u003cboard_target\u003e\n```\nIn order to show a list of all available board targets call:\n\n```Shell\nmake help\n```\n\nThis process might take a while. If everything goes well your fpga directory\nshould now contain two files:\n\n- `pulpissimo_\u003cboard_target\u003e.bit` the bitstream file for JTAG configuration of\n  the FPGA.\n- `pulpissimo_\u003cboard_target\u003e.bin` the binary configuration file to flash to a\n  non-volatile configuration memory.\n\n\nIf your invocation command to start Vivado isn't `vivado` you can use the Make\nvariable `VIVADO` to specify the right command (e.g. `make genesys2\nVIVADO='vitis vivado'` for ETH Almalinux machines.) Boot from ROM is not\navailable yet. The ROM will always return the `jal x0,0` to trap the core until\nthe debug module takes over control and loads the programm into L2 memory. Once\nthe bitstream `pulpissimo_genesys2.bit` is generated in the fpga folder, you can\nopen Vivado `vivado` (we tried the 2018.3 version) and load the bitstream into\nthe fpga or use the Configuration File (`pulpissimo_genesys2.bin`) to flash it\nto the on-board Configuration Memory.\n\n### Bitstream Flashing\nStart Vivado then:\n\n```\nOpen Hardware Manager\nOpen Target\nProgram device\n```\n\nNow your FPGA is ready to emulate PULPissimo!\n\n### Board Specific Information\nHave a look at the board specific README.md files in\n`target/fpga/pulpissimo-\u003cboard_target\u003e/README.md` for a description of peripheral\nmappings and default clock frequencies.\n\n### Compiling Applications for the FPGA Target\nTo run or debug applications for the FPGA you need to use a recent version of\nthe PULP-SDK (commit id 3256fe7 or newer.'). Configure the SDK for the FPGA\nplatform by running the following commands within the SDK's root directory:\n\n```Shell\nsource configs/pulpissimo.sh\nsource configs/fpgas/pulpissimo/\u003cboard_target\u003e.sh\n```\n**Currently, the only available board_target in the SDK is the genesys2.sh board. However, there are no board specific settings in this file except for the clock frequency and UART baudrate that can easily be overidden (see below). You can just source the genesys2.sh target regardless of which FPGA board you are actually using and override the frequencies and baudrate in your application. The only reason you need to source the genesys2.sh configuration file instead of e.g. the rtl platform configuration is to instruct the SDK to omit all runtime initialization (the code executed before your main function is called on the core) of the FLLs that are not available in the FPGA version of PULPissimo.**\n\nIf you updated the SDK don't forget to recompile the SDK and the dependencies.\n\nIn order for the SDK to be able to configure clock dividers (e.g. the ones for\nthe UART module) to the right values it needs to know which frequencies\nPULPissimo is running at. You can find the default frequencies in the above\nmentioned board specific README files.\n\nIn our application we need to override two weakly defined variables in our\nsource code to configure the SDK to use these frequencies:\n```C\n#include \u003cstdio.h\u003e\n#include \u003crt/rt_api.h\u003e\n\nint __rt_fpga_fc_frequency = \u003cCore Frequency\u003e // e.g. 20000000 for 20MHz;\nint __rt_fpga_periph_frequency = \u003cSoC Frequency\u003e // e.g. 10000000 for 10MHz;\n\nint main()\n{\n...\n}\n```\n\nBy default, the baudrate of the UART is set to `115200`.\n\nAdd the following global variable declaration to your application in case\nyou want to change it:\n\n```C\nunsigned int __rt_iodev_uart_baudrate = your baudrate;\n```\n\nCompile your application with\n\n```Shell\nmake clean all\n```\n\nThis command builds the ELF binary with UART as the default io peripheral.\nThe binary will be stored at `build/pulpissimo/[app_name]/[app_name]`.\n\n### Core selection\nBy default, PULPissimo is configured to use the RI5CY core with floating-point\nsupport being enabled. To switch to Ibex (and disable floating-point support),\nthe following steps need to be performed.\n\n1. Switch hardware configuration\n\n   Open the file `fpga/pulpissimo-\u003cboard_target\u003e/rtl/xilinx_pulpissimo.v` and\n   change the `CORE_TYPE` parameter to the preferred value. Change the value\n   of the `USE_FPU` parameter from `1` to `0`. Save the file and regenerate\n   the FPGA bitstream.\n\n2. Switch SDK configuration\n\n   Instead of sourcing `configs/pulpissimo.sh` when configuring the SDK,\n   source `configs/pulpissimo_ibex.sh`.\n\n### GDB and OpenOCD\nIn order to execute our application on the FPGA we need to load the binary into\nPULPissimo's L2 memory. To do so we can use OpenOCD in conjunction with GDB to\ncommunicate with the internal RISC-V debug module.\n\nPULPissimo uses JTAG as a communication channel between OpenOCD and the Core.\nHave a look at the board specific README file on how to connect your PC with\nPULPissimo's JTAG port.\n\nDue to a long outstanding issue in the RISC-V OpenOCD project (issue #359) the\nriscv/riscv-openocd does not work with PULPissimo. However there is a small\nworkaround that we incorporated in a patched version of openocd. If you have\naccess to the artifactory server, the patched openocd binary is installed by\ndefault with the `make deps` command in the SDK. If you don't have access to the\nprecompiled binaries you can automatically download and compile the patched\nOPENOCD from source. You will need to install the following dependencies on your\nmachine before you can compile OpenOCD:\n\n- `autoconf` \u003e= 2.64\n- `automake` \u003e= 1.14\n- `texinfo`\n- `make`\n- `libtool`\n- `pkg-config` \u003e= 0.23 (or compatible)\n- `libusb-1.0`\n- `libftdi`\n- `libusb-0.1` or `libusb-compat-0.1` for some older drivers\n\nAfter installing those dependecies with you OS' package manager you can\ndownload, apply the patch and compile OpenOCD with:\n\n```Shell\nsource sourceme.sh \u0026\u0026 ./pulp-tools/bin/plpbuild checkout build --p openocd --stdout\n```\n\nThe SDK will automatically set the environment variable `OPENOCD` to the\ninstallation path of this patched version.\n\nLaunch openocd with one of the provided or your own configuration file for the\ntarget board as an argument.\n\nE.g.:\n\n```Shell\n$OPENOCD/bin/openocd -f pulpissimo/fpga/pulpissimo-genesys2/openocd-genesys2.cfg\n```\nIn a seperate terminal launch gdb from your `pulp_riscv_gcc` installation passing\nthe ELF file as an argument with:\n\n`$PULP_RISCV_GCC_TOOLCHAIN_CI/bin/riscv32-unknown-elf-gdb  PATH_TO_YOUR_ELF_FILE`\n\nIn gdb, run:\n\n```\n(gdb) target remote localhost:3333\n```\n\nto connect to the OpenOCD server.\n\nIn a third terminal launch a serial port client (e.g. `screen` or `minicom`) on\nLinux to riderect the UART output from PULPissimo with e.g.:\n\n```Shell\nscreen /dev/ttyUSB0 115200\n```\n\nthe ttyUSB0 target may change.\n\nNow you are ready to debug!\n\nIn gdb, load the program into L2:\n\n```\n(gdb) load\n```\nand run the programm:\n\n```\n(gdb) continue\n```\nOf course you can also benefit from the debug capabilities that GDB provides.\n\nE.g. see the disasembled binary:\n```\n(gdb) disas\n```\nList the current C function, set a break point at line 25, continue and have fun!\n\n```\n(gdb) list\n21\n22  int main()\n23  {\n24    while (1) {\n25      printf(\"Hello World!\\n\\r\");\n26     for (volatile int i=0; i\u003c1000000; i++);\n27    }\n28    return 0;\n29  }\n\n(gdb) b 25\nBreakpoint 1 at 0x1c0083d2: file test.c, line 25.\n(gdb) c\nContinuing.\n\nBreakpoint 1, main () at test.c:25\n25      printf(\"Hello World!\\n\\r\");\n\n\n(gdb) disas\nDump of assembler code for function main:\n   0x1c0083d4 \u003c+22\u003e:    li  a1,1\n   0x1c0083d6 \u003c+24\u003e:    blt s0,a5,0x1c0083e8 \u003cmain+42\u003e\n=\u003e 0x1c0083da \u003c+28\u003e:    lw  a5,12(sp)\n   0x1c0083dc \u003c+30\u003e:    slli    a1,a1,0x1\n   0x1c0083de \u003c+32\u003e:    addi    a5,a5,1\n   0x1c0083e0 \u003c+34\u003e:    sw  a5,12(sp)\n\n(gdb) monitor reg a5\na5 (/32): 0x000075B7\n\n```\nNot all gdb commands work as expected on the riscv-dbg target.\nTo get a list of available gdb commands execute:\n```\nmonitor help\n```\n\nMost notably the command `info registers` does not work. Use `monitor reg`\ninstead which has the same effect.\n\n\n## Proprietary verification IPs\nThe full simulation platform can take advantage of a few models of commercial\nSPI, I2C, I2S peripherals to attach to the open-source PULP simulation platform.\nIn `target/sim/vip/spi_flash`, `target/sim/vip/i2c_eeprom`, `target/sim/vip/i2s`\nyou find the instructions to install SPI, I2C and I2S models.\n\nWhen the SPI flash model is installed, it will be possible to switch to a more\nrealistic boot simulation, where the internal ROM of PULP is used to perform an\ninitial boot and to start to autonomously fetch the program from the SPI flash.\nTo do this, the `LOAD_L2` parameter of the testbench has to be switched from\n`JTAG` to `STANDALONE`.\n\n## PULP platform structure\nAfter being fully setup as explained in the Getting Started section, this root\nrepository is structured as follows:\n- `target/sim/tb` contains the main platform testbench and the related files.\n- `target/sim/vip` contains the verification IPs used to emulate external peripherals,\n  e.g. SPI flash and camera.\n- `hw` could also contain other material (e.g. global includes, top-level\n  files)\n- `target/sim/questasim` contains the ModelSim/QuestaSim simulation platform.\n- `sw/pulp-runtime` contains the PULP runtime; `sw/regression_tests`\n  contains some tests released with the SDK or runtime. Some tests, especially\n  parallel tests, are not compatible with PULPissimo.\n- `Bender.yml` contains the package information used with bender. This includes\n  a list of IPs required and source files contained within this repository.\n- When using bender, other files may be relevant: `Bender.local` contains\n  configs for bender, including overrides for dependencies, `Bender.lock` is a\n  generated file used by bender, `utils/bin/bender` is the bender executable\n  fetched by the makefile, `.bender` directory contains the database and\n  checkouts used by bender.\n\n## Requirements\nThe RTL platform has the following requirements:\n- Relatively recent Linux-based operating system; we tested *Ubuntu 16.04*,\n  *CentOS 7*, and *Almalinux 8*.\n- QuestaSim in reasonably recent version (we tested it with version *2023.4*\n-- the free version provided by Altera is only partially working, see issue #12).\n- Python 3.4, with the `pyyaml` module installed (you can get that with\n  `pip3 install pyyaml`).\n- The SDK has its own dependencies, listed in\n  https://github.com/pulp-platform/pulp-sdk/blob/master/README.md\n- You will need the minicom command line application to view UART output in case\n  you use the 'run' Makefile target with the FPGA platform (discouraged, you\n  better use the approach outlined above)\n\n## External contributions\nThe supported way to provide external contributions is by forking one of our\nrepositories, applying your patch and submitting a pull request where you\ndescribe your changes in detail, along with motivations.\nThe pull request will be evaluated and checked with our regression test suite\nfor possible integration.\nIf you want to replace our version of an IP with your GitHub fork, just \nupdate the Bender.yml file and run `./utils/bin/bender update`.\nWhile we are quite relaxed in terms of coding style, please try to follow these\nrecommendations:\nhttps://github.com/pulp-platform/ariane/blob/master/CONTRIBUTING.md\n\n## Known issues\n\n## Support \u0026 Questions\nFor support on any issue related to this platform or any of the IPs, please add\nan issue to our tracker on https://github.com/pulp-platform/pulpissimo/issues\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Fpulpissimo","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpulp-platform%2Fpulpissimo","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Fpulpissimo/lists"}