{"id":13599955,"url":"https://github.com/pulp-platform/riscv-dbg","last_synced_at":"2026-03-03T07:36:06.099Z","repository":{"id":37663907,"uuid":"167359198","full_name":"pulp-platform/riscv-dbg","owner":"pulp-platform","description":"RISC-V Debug Support for our PULP RISC-V Cores","archived":false,"fork":false,"pushed_at":"2024-08-15T14:46:32.000Z","size":445,"stargazers_count":224,"open_issues_count":33,"forks_count":72,"subscribers_count":20,"default_branch":"master","last_synced_at":"2024-11-07T01:39:55.569Z","etag":null,"topics":["debug","riscv"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/pulp-platform.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-01-24T11:49:31.000Z","updated_at":"2024-10-24T16:35:55.000Z","dependencies_parsed_at":"2023-01-20T21:17:11.821Z","dependency_job_id":"3604c2fb-8131-400e-8476-5f103a7040c1","html_url":"https://github.com/pulp-platform/riscv-dbg","commit_stats":null,"previous_names":[],"tags_count":17,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Friscv-dbg","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Friscv-dbg/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Friscv-dbg/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Friscv-dbg/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/pulp-platform","download_url":"https://codeload.github.com/pulp-platform/riscv-dbg/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248261995,"owners_count":21074229,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["debug","riscv"],"created_at":"2024-08-01T17:01:21.197Z","updated_at":"2026-03-03T07:36:06.006Z","avatar_url":"https://github.com/pulp-platform.png","language":"SystemVerilog","funding_links":[],"categories":["SystemVerilog"],"sub_categories":[],"readme":"# RISC-V Debug Support for various Cores\n\nThis module is an implementation of a debug unit compliant with the [RISC-V\ndebug specification](https://github.com/riscv/riscv-debug-spec) v0.13.1. It is\nused in the [cva6](https://github.com/pulp-platform/cva6),\n[cv32e40p](https://github.com/pulp-platform/cv32e40p) and\n[ibex](https://github.com/lowRISC/ibex) cores.\n\n## Implementation\nWe use an execution-based technique, also described in the specification, where\nthe core is running in a \"park loop\". Depending on the request made to the debug\nunit via JTAG over the Debug Transport Module (DTM), the code that is being\nexecuted is changed dynamically. This approach simplifies the implementation\nside of the core, but means that the core is in fact always busy looping while\ndebugging.\n\n## Features\nThe following features are currently supported\n\n* Parametrizable buswidth for `XLEN=32` `XLEN=64` cores\n* Accessing registers over abstract command\n* Program buffer\n* System bus access (only `XLEN`)\n* DTM with JTAG interface\n\nThese are not implemented (yet)\n\n* Trigger module\n* Quick access using abstract commands\n* Accessing memory using abstract commands\n* Authentication\n\n## Limitations\n* The JTAG clock frequency needs to be lower than the system's clock frequency (see also https://github.com/pulp-platform/riscv-dbg/issues/163). \n\n## Tests\n\nWe use OpenOCD's [RISC-V compliance\ntests](https://github.com/riscv/riscv-openocd/blob/riscv/src/target/riscv/riscv-013.c),\nour custom testbench in `tb/` and\n[riscv-tests/debug](https://github.com/riscv/riscv-tests/tree/master/debug).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Friscv-dbg","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpulp-platform%2Friscv-dbg","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Friscv-dbg/lists"}