{"id":44052311,"url":"https://github.com/pulp-platform/snitch_cluster","last_synced_at":"2026-02-07T23:36:03.103Z","repository":{"id":176577374,"uuid":"617527938","full_name":"pulp-platform/snitch_cluster","owner":"pulp-platform","description":"An energy-efficient RISC-V floating-point compute cluster.","archived":false,"fork":false,"pushed_at":"2026-01-12T14:56:54.000Z","size":34385,"stargazers_count":121,"open_issues_count":17,"forks_count":94,"subscribers_count":7,"default_branch":"main","last_synced_at":"2026-01-12T19:49:00.205Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"https://pulp-platform.github.io/snitch_cluster/","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/pulp-platform.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":".github/CODEOWNERS","security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2023-03-22T15:18:43.000Z","updated_at":"2026-01-12T14:36:17.000Z","dependencies_parsed_at":"2023-10-22T19:28:23.175Z","dependency_job_id":"1aa4aedc-40e6-4984-840f-5a90ae23412b","html_url":"https://github.com/pulp-platform/snitch_cluster","commit_stats":null,"previous_names":["pulp-platform/snitch_cluster"],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/pulp-platform/snitch_cluster","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fsnitch_cluster","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fsnitch_cluster/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fsnitch_cluster/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fsnitch_cluster/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/pulp-platform","download_url":"https://codeload.github.com/pulp-platform/snitch_cluster/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pulp-platform%2Fsnitch_cluster/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29212754,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-07T23:14:30.912Z","status":"ssl_error","status_checked_at":"2026-02-07T23:14:17.253Z","response_time":63,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2026-02-07T23:36:02.525Z","updated_at":"2026-02-07T23:36:03.095Z","avatar_url":"https://github.com/pulp-platform.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"![CI](https://github.com/pulp-platform/snitch_cluster/actions/workflows/ci.yml/badge.svg)\n[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0)\n\n# Snitch Cluster\n\nThis repository hosts the hardware and software for the Snitch cluster and its generator. Snitch is a high-efficiency compute cluster platform focused on floating-point workloads. It is developed as part of the PULP project, a joint effort between ETH Zurich and the University of Bologna.\n\n## Getting Started\n\nTo get started working with Snitch check out our [documentation pages](https://pulp-platform.github.io/snitch_cluster). The documentation is built from the latest commit on the main branch.\n\n## Content\n\nWhat can you expect to find in this repository?\n\n- The RISC-V [Snitch integer core](https://pulp-platform.github.io/snitch_cluster/rm/hw/snitch.html). This can be useful stand-alone if you are just interested in re-using the core for your project, e.g., as a tiny control core or you want to make a peripheral smart. The sky is the limit.\n- The [Snitch cluster](https://pulp-platform.github.io/snitch_cluster/rm/hw/snitch_cluster.html). A highly configurable cluster containing one to many integer cores with optional floating-point capabilities as well as our custom ISA extensions `Xssr`, `Xfrep`, and `Xdma`.\n- A runtime and example applications for the Snitch cluster.\n- RTL simulation environments for Verilator, Questa Advanced Simulator, and VCS, as well as configurations for the [GVSoC system simulator](https://github.com/gvsoc/gvsoc).\n\nThis code was previously hosted in the [Snitch monorepo](https://github.com/pulp-platform/snitch) and was spun off into its own repository to simplify maintenance and dependency handling. Note that our Snitch-based manycore system [Occamy](https://github.com/pulp-platform/occamy) has also moved.\n\n## License\n\nSnitch is being made available under permissive open source licenses.\n\nThe following files are released under Solderpad v0.51 (`SHL-0.51`) see `hw/LICENSE`:\n\n- `hw/`\n\nThe `sw/deps` directory references submodules that come with their own\nlicenses. See the respective folder for the licenses used.\n\n- `sw/deps/`\n\nAll other files are released under Apache License 2.0 (`Apache-2.0`) see `LICENSE`.\n\n## Contributing\n\nIf you would like to contribute to this project, please check our [contribution guidelines](CONTRIBUTING.md).\n\n\n## Publications\n\n\u003c!--start-publications--\u003e\n\nIf you use the Snitch cluster or its extensions in your work, you can cite us:\n\n\u003cdetails\u003e\n\u003csummary\u003e\u003cb\u003e\u003ca href=\"https://doi.org/10.1109/TC.2020.3027900\"\u003eSnitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads\u003c/a\u003e\u003c/a\u003e\u003c/b\u003e\u003c/summary\u003e\n\u003cp\u003e\n\n```\n@ARTICLE{zaruba2021snitch,\n  author={Zaruba, Florian and Schuiki, Fabian and Hoefler, Torsten and Benini, Luca},\n  journal={IEEE Transactions on Computers}, \n  title={Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads}, \n  year={2021},\n  volume={70},\n  number={11},\n  pages={1845-1860},\n  doi={10.1109/TC.2020.3027900}\n}\n```\n\n\u003c/p\u003e\n\u003c/details\u003e\n\n\u003cdetails\u003e\n\u003csummary\u003e\u003cb\u003e\u003ca href=\"https://doi.org/10.1109/TC.2020.2987314\"\u003eStream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores\u003c/a\u003e\u003c/b\u003e\u003c/summary\u003e\n\u003cp\u003e\n\n```\n@ARTICLE{schuiki2021ssr,\n  author={Schuiki, Fabian and Zaruba, Florian and Hoefler, Torsten and Benini, Luca},\n  journal={IEEE Transactions on Computers}, \n  title={Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores}, \n  year={2021},\n  volume={70},\n  number={2},\n  pages={212-227},\n  doi={10.1109/TC.2020.2987314}\n}\n```\n\n\u003c/p\u003e\n\u003c/details\u003e\n\n\u003cdetails\u003e\n\u003csummary\u003e\u003cb\u003e\u003ca href=\"https://doi.org/10.1109/TPDS.2023.3322029\"\u003eSparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra\u003c/a\u003e\u003c/b\u003e\u003c/summary\u003e\n\u003cp\u003e\n\n```\n@ARTICLE{scheffler2023sparsessr,\n  author={Scheffler, Paul and Zaruba, Florian and Schuiki, Fabian and Hoefler, Torsten and Benini, Luca},\n  journal={IEEE Transactions on Parallel and Distributed Systems}, \n  title={Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra}, \n  year={2023},\n  volume={34},\n  number={12},\n  pages={3147-3161},\n  doi={10.1109/TPDS.2023.3322029}\n}\n```\n\n\u003c/p\u003e\n\u003c/details\u003e\n\n\u003cdetails\u003e\n\u003csummary\u003e\u003cb\u003e\u003ca href=\"https://doi.org/10.1109/TC.2023.3329930\"\u003eA High-Performance, Energy-Efficient Modular DMA Engine Architecture\u003c/a\u003e\u003c/b\u003e\u003c/summary\u003e\n\u003cp\u003e\n\n```\n@ARTICLE{benz2024idma,\n  author={Benz, Thomas and Rogenmoser, Michael and Scheffler, Paul and Riedel, Samuel and Ottaviano, Alessandro and Kurth, Andreas and Hoefler, Torsten and Benini, Luca},\n  journal={IEEE Transactions on Computers}, \n  title={A High-Performance, Energy-Efficient Modular DMA Engine Architecture}, \n  year={2024},\n  volume={73},\n  number={1},\n  pages={263-277},\n  doi={10.1109/TC.2023.3329930}\n}\n```\n\n\u003c/p\u003e\n\u003c/details\u003e\n\n\u003cdetails\u003e\n\u003csummary\u003e\u003cb\u003e\u003ca href=\"https://doi.org/10.1109/ARITH54963.2022.00010\"\u003eMiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores\u003c/a\u003e\u003c/b\u003e\u003c/summary\u003e\n\u003cp\u003e\n\n```\n@INPROCEEDINGS{bertaccini2022minifloat,\n  author={Bertaccini, Luca and Paulin, Gianna and Fischer, Tim and Mach, Stefan and Benini, Luca},\n  booktitle={2022 IEEE 29th Symposium on Computer Arithmetic (ARITH)}, \n  title={MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores}, \n  year={2022},\n  volume={},\n  number={},\n  pages={1-8},\n  doi={10.1109/ARITH54963.2022.00010}\n}\n```\n\n\u003c/p\u003e\n\u003c/details\u003e\n\n\u003cdetails\u003e\n\u003csummary\u003e\u003cb\u003e\u003ca href=\"https://doi.org/10.1109/ISVLSI54635.2022.00021\"\u003eSoft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters\u003c/a\u003e\u003c/b\u003e\u003c/summary\u003e\n\u003cp\u003e\n\n```\n@INPROCEEDINGS{paulin2022softtiles,\n  author={Paulin, Gianna and Cavalcante, Matheus and Scheffler, Paul and Bertaccini, Luca and Zhang, Yichao and Gürkaynak, Frank and Benini, Luca},\n  booktitle={2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, \n  title={Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters}, \n  year={2022},\n  volume={},\n  number={},\n  pages={44-49},\n  doi={10.1109/ISVLSI54635.2022.00021}\n}\n```\n\n\u003c/p\u003e\n\u003c/details\u003e\n\n\u003cdetails\u003e\n\u003csummary\u003e\u003cb\u003e\u003ca href=\"https://doi.org/10.1145/3649329.3658494\"\u003eSARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers\u003c/a\u003e\u003c/b\u003e\u003c/summary\u003e\n\u003cp\u003e\n\n```\n@INPROCEEDINGS{scheffler2024saris,\n  author={Paul Scheffler and Luca Colagrande and Luca Benini},\n  title={SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers},\n  booktitle = {Proceedings of the 61st ACM/IEEE Design Automation Conference},\n  year={2024},\n  doi = {10.1145/3649329.3658494}\n}\n```\n\n\u003c/p\u003e\n\u003c/details\u003e\n\n\u003cdetails\u003e\n\u003csummary\u003e\u003cb\u003e\u003ca href=\"https://arxiv.org/abs/2503.20590\"\u003eDual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores\u003c/a\u003e\u003c/b\u003e\u003c/summary\u003e\n\u003cp\u003e\n\n```\n@misc{colagrande2025copift,\n  title={Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores},\n  author={Luca Colagrande and Luca Benini},\n  year={2025},\n  eprint={2503.20590},\n  archivePrefix={arXiv},\n  primaryClass={cs.AR},\n  url={https://arxiv.org/abs/2503.20590}\n}\n```\n\n\u003c/p\u003e\n\u003c/details\u003e\n\n\u003cdetails\u003e\n\u003csummary\u003e\u003cb\u003e\u003ca href=\"https://arxiv.org/abs/2503.20609\"\u003eLate Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors\u003c/a\u003e\u003c/b\u003e\u003c/summary\u003e\n\u003cp\u003e\n\n```\n@misc{colagrande2025chaining,\n  title={Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors},\n  author={Luca Colagrande and Jayanth Jonnalagadda and Luca Benini},\n  year={2025},\n  eprint={2503.20609},\n  archivePrefix={arXiv},\n  primaryClass={cs.AR},\n  url={https://arxiv.org/abs/2503.20609}\n}\n```\n\n\u003c/p\u003e\n\u003c/details\u003e\n\n\u003c!--end-publications--\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Fsnitch_cluster","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpulp-platform%2Fsnitch_cluster","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulp-platform%2Fsnitch_cluster/lists"}