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align=\"center\"\u003e\n\n# Spar\n\n\u003csup\u003ea compiler for system-architecture models\u003c/sup\u003e\n\n\u0026nbsp;\n\n![Rust](https://img.shields.io/badge/Rust-CE422B?style=flat-square\u0026logo=rust\u0026logoColor=white\u0026labelColor=1a1b27)\n![WebAssembly](https://img.shields.io/badge/WebAssembly-654FF0?style=flat-square\u0026logo=webassembly\u0026logoColor=white\u0026labelColor=1a1b27)\n![AADL](https://img.shields.io/badge/AADL_v2.3-AS5506D-654FF0?style=flat-square\u0026labelColor=1a1b27)\n![SysML](https://img.shields.io/badge/SysML_v2-KerML-654FF0?style=flat-square\u0026labelColor=1a1b27)\n![TSN](https://img.shields.io/badge/TSN-Network_Calculus-654FF0?style=flat-square\u0026labelColor=1a1b27)\n![License: MIT](https://img.shields.io/badge/License-MIT-blue?style=flat-square\u0026labelColor=1a1b27)\n\n[![CI](https://github.com/pulseengine/spar/actions/workflows/ci.yml/badge.svg)](https://github.com/pulseengine/spar/actions/workflows/ci.yml)\n[![Lean Proofs](https://github.com/pulseengine/spar/actions/workflows/proofs.yml/badge.svg)](https://github.com/pulseengine/spar/actions/workflows/proofs.yml)\n[![Rivet validate](https://img.shields.io/github/actions/workflow/status/pulseengine/spar/ci.yml?branch=main\u0026label=rivet%20validate\u0026logo=githubactions\u0026logoColor=white)](https://github.com/pulseengine/spar/actions/workflows/ci.yml)\n[![codecov](https://codecov.io/gh/pulseengine/spar/graph/badge.svg)](https://codecov.io/gh/pulseengine/spar)\n\n\u0026nbsp;\n\n\u003ch6\u003e\n  \u003ca href=\"https://github.com/pulseengine/meld\"\u003eMeld\u003c/a\u003e\n  \u0026middot;\n  \u003ca href=\"https://github.com/pulseengine/loom\"\u003eLoom\u003c/a\u003e\n  \u0026middot;\n  \u003ca href=\"https://github.com/pulseengine/synth\"\u003eSynth\u003c/a\u003e\n  \u0026middot;\n  \u003ca href=\"https://github.com/pulseengine/kiln\"\u003eKiln\u003c/a\u003e\n  \u0026middot;\n  \u003ca href=\"https://github.com/pulseengine/sigil\"\u003eSigil\u003c/a\u003e\n  \u0026middot;\n  \u003ca href=\"https://github.com/pulseengine/spar\"\u003eSpar\u003c/a\u003e\n\u003c/h6\u003e\n\n\u003c/div\u003e\n\n\u0026nbsp;\n\nSpar is a **compiler for system-architecture models**, built on rust-analyzer's proven\narchitecture patterns. Like a programming-language compiler it has *front-ends* (parsers for\nseveral modelling formalisms), a shared *intermediate representation* (an incremental,\nsalsa-backed HIR), a *middle-end* of analyses, and *back-ends* that emit code and diagrams —\nexcept the \"programs\" it compiles are **system architectures**.\n\n- **Front-ends — multi-formalism ingest.** AADL v2.3 (SAE AS5506D), SysML v2 / KerML, and\n  CAN `.dbc` networks all lower into one semantic model. ARXML (AUTOSAR) is on the roadmap.\n- **Middle-end — analysis \u0026 timing.** 30+ pluggable passes (scheduling, EMV2 fault trees,\n  ARINC 653 partitioning, ASIL decomposition, resource budgets) plus a real-time\n  **network-calculus** engine (TFA / PLP) that computes worst-case TSN/Ethernet latency bounds —\n  the kind of timing analysis usually reserved for tools like tsnkit, RTaW-Pegase or pegase.\n- **Back-ends — generate \u0026 visualize.** WIT/WASM components, Lean 4 and Kani proof skeletons,\n  Bazel build files, SVG and Mermaid architecture diagrams.\n- **Verified by construction.** Every capability is traced to a requirement (rivet artifacts),\n  oracle-gated in CI, and exposed read-only to AI agents over MCP.\n\nThis is why it has outgrown the \"AADL toolchain\" label: AADL is one of several front-ends, and\nthe timing/verification middle-end is a substrate any architecture formalism can feed. Spar\nreplaces the Eclipse/Java OSATE2 toolchain with a fast, embeddable, WASM-compilable alternative —\nand reaches well past what OSATE, or a single-formalism SysML v2 tool, covers.\n\n## Components\n\n```mermaid\nflowchart TB\n    subgraph FE[\"Front-ends · multi-formalism ingest\"]\n        AADL[\"spar-parser · spar-syntax · spar-annex\u003cbr/\u003eAADL v2.3 — lossless CST + annexes (EMV2, BA)\"]\n        SYSML[\"spar-sysml2\u003cbr/\u003eSysML v2 / KerML → AADL lowering\"]\n        DBC[\"spar-dbc\u003cbr/\u003eCAN .dbc → AADL\"]\n    end\n\n    subgraph IR[\"Semantic core · incremental IR\"]\n        DB[\"spar-base-db\u003cbr/\u003esalsa incremental DB\"]\n        HIRDEF[\"spar-hir-def\u003cbr/\u003eitem tree · instance model\"]\n        HIR[\"spar-hir\u003cbr/\u003esemantic facade\"]\n        VAR[\"spar-variants\u003cbr/\u003eproduct-line / variant filtering\"]\n    end\n\n    subgraph MID[\"Middle-end · analysis \u0026 timing\"]\n        ANL[\"spar-analysis\u003cbr/\u003e30+ passes: scheduling, EMV2 fault trees,\u003cbr/\u003eARINC 653, ASIL, budgets\"]\n        NET[\"spar-network\u003cbr/\u003eNetwork Calculus TFA / PLP\u003cbr/\u003eTSN / Ethernet WCTT bounds\"]\n        SOL[\"spar-solver\u003cbr/\u003ethread→processor deployment\"]\n        TOPO[\"spar-trace-topology\u003cbr/\u003ePCAPNG+LLDP vs declared topology\"]\n        INS[\"spar-insight\u003cbr/\u003eCTF trace vs predicted timing\"]\n    end\n\n    subgraph BE[\"Back-ends · generate \u0026 visualize\"]\n        GEN[\"spar-codegen\u003cbr/\u003eWIT · Rust · Lean 4 · Kani · Bazel\"]\n        TR[\"spar-transform\u003cbr/\u003eAADL ↔ WIT / WAC / wRPC\"]\n        REN[\"spar-render\u003cbr/\u003eSVG (Sugiyama layout)\"]\n        MMD[\"spar-mermaid\u003cbr/\u003eMermaid diagrams\"]\n    end\n\n    subgraph IF[\"Interfaces\"]\n        CLI[\"spar-cli\u003cbr/\u003e16 subcommands incl. LSP + MCP\"]\n        MCP[\"spar-mcp\u003cbr/\u003eread-only oracles for AI agents\"]\n        WASM[\"spar-wasm\u003cbr/\u003eWASI P2 / browser component\"]\n    end\n\n    VFY[\"spar-verify · spar-verify-macros\u003cbr/\u003erequirements assertion engine\"]\n\n    AADL --\u003e DB\n    SYSML --\u003e DB\n    DBC --\u003e DB\n    DB --\u003e HIRDEF --\u003e HIR --\u003e VAR\n    HIR --\u003e ANL\n    HIR --\u003e NET\n    HIR --\u003e SOL\n    HIR --\u003e TOPO\n    HIR --\u003e INS\n    ANL --\u003e VFY\n    NET --\u003e VFY\n    HIR --\u003e GEN\n    HIR --\u003e TR\n    HIR --\u003e REN\n    HIR --\u003e MMD\n    CLI --\u003e HIR\n    MCP --\u003e HIR\n    WASM --\u003e HIR\n    GEN --\u003e|WIT components| DOWN[\"PulseEngine chain →\u003cbr/\u003ewitness · sigil · smithy · loom\"]\n```\n\n## Installation\n\n```bash\n# From source\ncargo install --git https://github.com/pulseengine/spar\n\n# Or download a pre-built binary from releases\n# https://github.com/pulseengine/spar/releases\n```\n\n## Quick Start\n\n```bash\n# Parse an AADL model and show the syntax tree\nspar parse vehicle.aadl --tree\n\n# List all declared items\nspar items vehicle.aadl\n\n# Instantiate a system hierarchy\nspar instance --root Pkg::System.Impl vehicle.aadl test-data/sensor_lib.aadl\n\n# Run all analysis passes\nspar analyze --root Pkg::System.Impl vehicle.aadl test-data/sensor_lib.aadl\n\n# Allocate threads to processors (deployment solver)\nspar allocate --root Pkg::System.Impl vehicle.aadl test-data/sensor_lib.aadl\n\n# Render the architecture as SVG\nspar render --root Pkg::System.Impl -o arch.svg vehicle.aadl test-data/sensor_lib.aadl\n\n# Run verification assertions\nspar verify --root Pkg::System.Impl --rules rules.toml vehicle.aadl\n```\n\n## CLI Commands\n\n| Command    | Description                                                  |\n|------------|--------------------------------------------------------------|\n| `parse`    | Parse AADL files and show syntax tree or errors              |\n| `items`    | List declared packages, types, implementations               |\n| `instance` | Build the system instance hierarchy                          |\n| `analyze`  | Run all analysis passes (SARIF/JSON/text output)             |\n| `allocate` | Solve thread-to-processor deployment bindings                |\n| `diff`     | Compare two model versions for structural/diagnostic changes |\n| `modes`    | Mode reachability analysis and SMV/DOT export                |\n| `emit`     | Emit a Mermaid flowchart from an instantiated system         |\n| `render`   | Generate SVG/HTML architecture diagrams                      |\n| `verify`   | Evaluate verification assertions against the model           |\n| `codegen`  | Generate code (WIT/Rust/Lean4/Kani/Bazel) from an instance   |\n| `dbc`      | Ingest a CAN `.dbc` file and emit AADL (bus + devices)       |\n| `moves`    | Hypothetical-rebinding oracle (verify a move under overlay)  |\n| `insight`  | Compare CTF timing traces to Expected_BCET/WCET/Mean         |\n| `lsp`      | Start the Language Server Protocol server                    |\n| `mcp`      | Start the MCP server (read-only oracles for AI agents)       |\n\n## Architecture\n\n23 crates, organized as compiler stages — front-ends → IR → middle-end → back-ends:\n\n```\nFront-ends (ingest)\n  spar-syntax         Lossless CST (rowan red-green trees) + typed AST\n  spar-parser         AADL recursive-descent parser with error recovery\n  spar-annex          AADL annex sublanguages (EMV2, BA, BLESS)\n  spar-sysml2         SysML v2 / KerML parser + AADL lowering + requirements\n  spar-dbc            CAN .dbc ingest -\u003e AADL source text\n\nSemantic core (intermediate representation)\n  spar-base-db        Salsa database for incremental computation\n  spar-hir-def        HIR definitions -- item tree, instance model, arenas\n  spar-hir            Public semantic facade (name resolution, properties)\n  spar-variants       Product-line variant selection and HIR filtering\n\nMiddle-end (analysis \u0026 timing)\n  spar-analysis       30+ pluggable analysis passes\n  spar-network        Network Calculus (TFA/PLP) -- TSN/Ethernet WCTT bounds\n  spar-solver         Deployment solver (thread-to-processor allocation)\n  spar-trace-topology Runtime vs declared topology (PCAPNG + LLDP + Qcc)\n  spar-insight        Discrepancy assistant (CTF traces vs predicted timing)\n\nVerification\n  spar-verify         Requirements verification / assertion engine\n  spar-verify-macros  Procedural macros for verification rules\n\nBack-ends (generate \u0026 visualize)\n  spar-codegen        Codegen from instance models (WIT, Rust, Lean4, Kani, Bazel)\n  spar-transform      Format transforms (AADL \u003c-\u003e WIT, WAC, wRPC)\n  spar-render         SVG architecture diagrams (compound Sugiyama layout)\n  spar-mermaid        Mermaid diagram emission\n\nInterfaces\n  spar-cli            Command-line interface (16 subcommands incl. LSP + MCP)\n  spar-mcp            Model Context Protocol server (read-only oracles)\n  spar-wasm           WebAssembly component (WASI P2 / browser)\n```\n\n## Key Features\n\n- **Multi-formalism ingest** -- AADL v2.3, SysML v2 / KerML, and CAN `.dbc` all lower into one semantic model (ARXML on the roadmap)\n- **30+ analysis passes** -- scheduling, latency, connectivity, resource budgets, ARINC 653, ASIL, EMV2 fault trees, bus bandwidth, weight/power, mode reachability, and more\n- **Network-calculus timing** -- worst-case TSN/Ethernet latency bounds via Total-Flow (TFA) and Polynomial-LP (PLP) analysis, cross-validated against the panco reference ([Bouillard](https://arxiv.org/abs/2010.09263))\n- **Assertion engine** -- declarative verification rules in TOML (`spar verify`)\n- **Deployment solver** -- automated thread-to-processor allocation with constraint satisfaction\n- **Code generation** -- WIT/WASM components, Lean 4 + Kani proof skeletons, Bazel build files\n- **AI-agent native** -- read-only verification oracles exposed over MCP (`spar mcp`)\n- **SARIF output** -- analysis results in SARIF format for CI integration\n- **VS Code extension** -- live rendering and diagnostics via LSP\n- **WASM component** -- compiles to a wasm32-wasip2 component\n- **Incremental** -- salsa-based memoization for fast re-analysis\n- **Lossless parsing** -- every byte preserved in the syntax tree\n\n## Editor support\n\nA first-party VS Code extension lives in [`vscode-spar/`](vscode-spar/). It pairs the `spar lsp` server (diagnostics, hover, go-to-definition, completion, rename, inlay hints) with a live architecture-diagram webview that re-renders on save. See [`vscode-spar/README.md`](vscode-spar/README.md) for install + setup.\n\n## Documentation\n\n- [Quickstart](docs/quickstart.md) -- build spar, parse + analyze the sample model in ~30 minutes\n- [`spar moves` reference](docs/cli/moves.md) -- hypothetical-rebinding oracle (verify + enumerate)\n- [WASM-as-architecture design](docs/plans/2026-03-10-wasm-as-architecture-design.md) -- WIT/WAC/wRPC transforms\n- [VS Code extension design](docs/plans/2026-03-18-vscode-extension-design.md) -- editor integration\n- [Deployment solver plan](docs/plans/2026-03-21-deployment-solver-plan.md) -- allocation algorithm\n\n## Safety\n\nFull STPA (System-Theoretic Process Analysis) safety analysis:\n\n- [STPA analysis](safety/stpa/analysis.yaml) -- losses, hazards, UCAs, loss scenarios\n- [Safety requirements](safety/stpa/requirements.yaml) -- 23 STPA-derived requirements\n- [Rivet artifacts](artifacts/) -- requirements, architecture decisions, verification records\n\n## License\n\nMIT License -- see [LICENSE](LICENSE).\n\n---\n\n\u003cdiv align=\"center\"\u003e\n\n\u003csub\u003ePart of \u003ca href=\"https://github.com/pulseengine\"\u003ePulseEngine\u003c/a\u003e -- formally verified WebAssembly toolchain for safety-critical systems\u003c/sub\u003e\n\n\u003c/div\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulseengine%2Fspar","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpulseengine%2Fspar","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpulseengine%2Fspar/lists"}