{"id":23950913,"url":"https://github.com/pvgupta24/von-neumann-architecture-cpu","last_synced_at":"2026-02-21T06:03:00.296Z","repository":{"id":67033150,"uuid":"108860014","full_name":"pvgupta24/Von-Neumann-Architecture-CPU","owner":"pvgupta24","description":"Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL ","archived":false,"fork":false,"pushed_at":"2017-11-16T10:10:17.000Z","size":209,"stargazers_count":6,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-10-30T16:19:33.118Z","etag":null,"topics":["cpu","cpu-simulator","verilog","verilog-hdl","von-neumann"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/pvgupta24.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2017-10-30T14:11:28.000Z","updated_at":"2025-05-26T14:01:20.000Z","dependencies_parsed_at":null,"dependency_job_id":"f7c0837c-8c69-467b-8fe4-08612a0f812f","html_url":"https://github.com/pvgupta24/Von-Neumann-Architecture-CPU","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/pvgupta24/Von-Neumann-Architecture-CPU","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pvgupta24%2FVon-Neumann-Architecture-CPU","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pvgupta24%2FVon-Neumann-Architecture-CPU/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pvgupta24%2FVon-Neumann-Architecture-CPU/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pvgupta24%2FVon-Neumann-Architecture-CPU/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/pvgupta24","download_url":"https://codeload.github.com/pvgupta24/Von-Neumann-Architecture-CPU/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/pvgupta24%2FVon-Neumann-Architecture-CPU/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29674933,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-21T05:54:28.202Z","status":"ssl_error","status_checked_at":"2026-02-21T05:53:42.585Z","response_time":107,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","cpu-simulator","verilog","verilog-hdl","von-neumann"],"created_at":"2025-01-06T12:57:51.811Z","updated_at":"2026-02-21T06:03:00.291Z","avatar_url":"https://github.com/pvgupta24.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"## 8-Bit Von Neumann Architecture CPU\n\n#### Contributors \n- Praveen Kumar Gupta\n- Durvesh Bhalekar\n\n### Abstract\n\u003e This verilog program shows the simulation of a 8-bit processor built on the principles of the Von Neumman architecture.\n\u003e The program can be loaded in the RAM module and the following code carries out the instructions accordingly. \n\n### Functionalities   \n\u003e This processor allows supported instructions (as given in the Instruction Set file) to be written in the RAM module.\n\n![Instruction Set](Instruc_Set.png)\n\n\u003e An Instruction cycle is broken into 3 phases - Fetch , Decode and Execute\n\n\u003e Instructions from RAM Module are fetched into the Instruction Register on the appropriate phase, it is decoded by the control unit which sets various flags and select lines depending on the type of instruction, like \n\n\u003e * fetching into immediate register\n\u003e * writing in register file\n\u003e * changing PC value\n\u003e * selecting address from imm. or PC\n\u003e * selecting the correct register from RF\n\u003e * Deciding the ALU operation\n\u003e * Sending the ALU output to the required place.\n\n\n## Software Requirements\n\n- Logisim\n- iverilog\n- gtkwave\n\n## Usage Instructions\n\n* Open either Behavioural or Dataflow Modelling Verilog file for CPU.\n\n* From the given Instruction Set table, write 8-Bit binary instructions\n  in the given RAM module at the end of the file.\n* Sample instructions are already present. Overwrite it if needed.\n\n* Enable Simulation.\n\n  Compile the file as\n\n        ` iverilog VerilogBM-210-235.v Verilog-210-235.v -o Verilog-210-235.vvp `\n\n  Run the vvp file as\n  \n        ` vvp Verilog-210-235.vvp ` \n\n  Open the output wave as\n  \n        ` gtkwave VerilogBM-210-235.vcd `\n\nCorresponding changes can be seen in the wave as per instructions.\n\n## References\n- Computer Organization and Design - Book by David Patterson and John Hennessy\n- [Computer Architechture Tutorials](http://minnie.tuhs.org/CompArch/Tutes/week03.html)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpvgupta24%2Fvon-neumann-architecture-cpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fpvgupta24%2Fvon-neumann-architecture-cpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fpvgupta24%2Fvon-neumann-architecture-cpu/lists"}