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**Multi-threading**: Hexagon-optimized parallel execution of operations for improved performance\n  - **Vector Processing**: Optimized code generation targeting Hexagon Vector eXtensions (HVX) units\n  - **TCM Utilization**: Leverage Tightly Coupled Memory (TCM) for reduced memory latency\n  - **DMA Optimization**: Efficient DMA transfers between DDR and TCM memory spaces\n  - **Matrix Processing (experimental)**: Leverage Qualcomm's Hexagon Kernel Library for matrix multiplication\n- **IR Inspection**: Inspect and analyze IR lowering passes, helping you understand how your code is optimized\n\n## Documentation\n- 📖 [User Guide](docs/user-guide.md) - For instructions on how to download, setup our compiler and start running Triton kernels or PyTorch models on Hexagon NPUs\n- 🎓 [Tutorials](docs/tutorials/README.md) - A set of tutorials on Triton kernels and PyTorch models\n- ❓ [FAQ](docs/faq.md) - Frequently asked questions\n- 🏗️ [Developer Guide](docs/developer-guide.md) - Insights on how to develop, debug and profile using our compiler toolchain for Triton kernels and PyTorch models\n\n## License\n\nCopyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n\n---\n\n\u003cdiv align=\"center\"\u003e\n  \u003csub\u003eBuilt with ❤️ by the  Hexagon-MLIR Team\u003c/sub\u003e\n\u003c/div\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fqualcomm%2Fhexagon-mlir","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fqualcomm%2Fhexagon-mlir","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fqualcomm%2Fhexagon-mlir/lists"}