{"id":19195271,"url":"https://github.com/quartiq/bscan_spi_bitstreams","last_synced_at":"2025-05-08T23:04:09.619Z","repository":{"id":35002209,"uuid":"39093542","full_name":"quartiq/bscan_spi_bitstreams","owner":"quartiq","description":"FPGA gateware and pre-build bitstreams that expose SPI over JTAG. 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These bitstreams have been tested on the [KC705](https://github.com/ntfreak/openocd/blob/master/tcl/board/kc705.cfg), [Pipistrello](https://github.com/ntfreak/openocd/blob/master/tcl/board/pipistrello.cfg), Kasli, Sayma-AMC+Sayma-RTM, Lattice ECP5 Versa and several other boards.\n\nCurrently, bitstreams for Xilinx and Lattice chips are generated with the following scripts:\n\n* [xilinx_bscan_spi.py](xilinx_bscan_spi.py): [**(o)Migen**](https://github.com/m-labs/migen/) script that generates bitstreams for Xilinx chips; all the generated `.bit` bistreams are contained in this repository.\n* [lattice_bscan_spi.py](lattice_bscan_spi.py): [**nMigen**](https://github.com/m-labs/nmigen/) script that generates bitstreams for Lattice chips; a `.svf` JTAG programming vector generated for LFE5UM-45F is currently contained in this repository.\n  * _Note on usage: After programming the device through JTAG, the `reset halt` command is required before performing flash commands on OpenOCD. Also note that when using jtagspi, the private instruction `0x32` must be shifted into the JTAG IR on Lattice FPGAs (see item \"ER1, ER2\" on p.758 of the [FPGA Libraries Reference Guide 3.11](http://www.latticesemi.com/view_document?document_id=52656) for details)._\n\n## Versions\n\n**Note**: The bitstreams in this branch require openocd as of [867bdb2](https://github.com/ntfreak/openocd/tree/867bdb2e9248a974f7db0a99fbe5d2dd8b46d25d) or later.\nSince 2017-08-08 and as of 2019-06-11 there has not been an openocd release including this.\n\n**Note**: Bitstreams for previous openocd releases are in the [single-tap](https://github.com/quartiq/bscan_spi_bitstreams/commits/single-tap) branch.\n\n## Run\n\n```\npython3 -m venv --system-site-packages .venv\n./.venv/bin/pip install -r requirements.txt\nPATH=$PATH:/opt/Xilinx/Vivado/2022.2/bin:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64 ./.venv/bin/python3 xilinx_bscan_spi.py -p 16\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fquartiq%2Fbscan_spi_bitstreams","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fquartiq%2Fbscan_spi_bitstreams","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fquartiq%2Fbscan_spi_bitstreams/lists"}