{"id":19195256,"url":"https://github.com/quartiq/fastino","last_synced_at":"2025-05-08T23:01:18.193Z","repository":{"id":83855343,"uuid":"208273139","full_name":"quartiq/fastino","owner":"quartiq","description":"Gateware and software for Fastino (32 channel 2.5 MS/s 16 bit DAC for the Sinara ecosystem)","archived":false,"fork":false,"pushed_at":"2023-03-02T20:32:05.000Z","size":119,"stargazers_count":4,"open_issues_count":5,"forks_count":2,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-05-08T07:46:43.227Z","etag":null,"topics":["artiq","dsp","fpga","migen","sinara-hw"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/quartiq.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.GPL-3","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2019-09-13T13:44:53.000Z","updated_at":"2023-09-24T10:10:38.000Z","dependencies_parsed_at":null,"dependency_job_id":"250ced6d-502b-405a-ab8b-46cc8b1e0bc4","html_url":"https://github.com/quartiq/fastino","commit_stats":null,"previous_names":[],"tags_count":2,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/quartiq%2Ffastino","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/quartiq%2Ffastino/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/quartiq%2Ffastino/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/quartiq%2Ffastino/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/quartiq","download_url":"https://codeload.github.com/quartiq/fastino/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253160764,"owners_count":21863627,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["artiq","dsp","fpga","migen","sinara-hw"],"created_at":"2024-11-09T12:09:19.396Z","updated_at":"2025-05-08T23:01:18.186Z","avatar_url":"https://github.com/quartiq.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"[![QUARTIQ Matrix Chat](https://img.shields.io/matrix/quartiq:matrix.org)](https://matrix.to/#/#quartiq:matrix.org)\n\n# Fastino gateware and software development\n\n* Fastino is a 32 channels, 2 M/s simultaneous, 16 bit DAC\n* [AD5542ABCPZ](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5512A_5542A.pdf)\n\n## Hardware\n\nHardware https://github.com/sinara-hw/Fastino/wiki\n\n## Link\n\n* Interface: single EEM\n    * CLK word clock at 250 MHz/7, 1:7 serialization/deserialization, and 3:4 clock duty cycle\n    * MOSI0 data 250 Mb/s, 125 MHz DDR bit clock\n    * MOSI1\n    * MOSI2\n    * MOSI3\n    * MOSI4\n    * MOSI5\n    * MISO return data at 125/7 Mb/s (TBD)\n* Each word (one word clock cycle with 7 bits per lane) is `7*6=42` bits.\n* A frame consists of 14 words.\n* A frame contains 14/2+1 marker bits to provide EOF alignment and a 12 bit CRC.\n* This leaves 568 bits per frame for `32*16` bits DAC data, a 32 bit channel\n  mask, and 24 bits for configuration and return data addressing\n* On 6 data lanes, this achieves 1.5 Gb/s raw from the FPGA and 1.45 Gb/s\n  net payload (after accounting for framing and checksum).\n* The frame period is 392 ns and the DAC data/sample/update rate is\n  therefore 2.55 MS/s.\n* There is one slower upstream lane at 125/7 Mb/s providing 7 bits per\n  frame return data. Details TBD\n* Similar to well-known video and highspeed/serdes data links\n* Link design benefits Grabber HITL testing\n* The Link design can be reused for Humpback and Banker where the same FPGA sits on the EEM.\n* Link training (bit slip, delay alignment) is automatic\n* Checksum protects the data\n* Due to the beat between the 7x4 ns word clock and the 21 ns SPI clock, there is a deterministic jitter in the DAC conversion with an amplitude of 7 ns and a period of 3 samples.\n\n### Tools\n\n* migen\n* misoc\n* yosys\n* nextpnr\n* icestorm\n\n### Build\n\n* If using an old nextpnr version, patch migen to use the `heap` placer\n\n```\npython fastino_phy.py\n```\n\n### Flash\n\nSee https://github.com/quartiq/kasli-i2c\n\nFigure out the `aa-bb-cc-dd-ee-ff` mac address of the Kasli connected. Otherwise\nif you are using a Kasli that was not provisioned using the tools in `kasli-i2c`,\npatch `flash_fastino.py` to make it find your Kasli. Assuming Fastino is\nconnected to EEM0:\n\n```\npython flash_fastino.py aa-bb-cc-dd-ee-ff EEM0 write fastino.bin\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fquartiq%2Ffastino","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fquartiq%2Ffastino","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fquartiq%2Ffastino/lists"}