{"id":19195253,"url":"https://github.com/quartiq/phaser","last_synced_at":"2025-05-08T23:01:43.530Z","repository":{"id":37088244,"uuid":"215786147","full_name":"quartiq/phaser","owner":"quartiq","description":"Phaser AWG DSP design","archived":false,"fork":false,"pushed_at":"2025-05-06T10:54:17.000Z","size":7333,"stargazers_count":11,"open_issues_count":3,"forks_count":7,"subscribers_count":7,"default_branch":"master","last_synced_at":"2025-05-08T07:46:44.110Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Jupyter Notebook","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/quartiq.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.GPL-3","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2019-10-17T12:24:11.000Z","updated_at":"2025-05-06T10:54:21.000Z","dependencies_parsed_at":"2025-04-20T09:42:29.556Z","dependency_job_id":"64eb0527-802d-4a41-8681-5b2f37e30e02","html_url":"https://github.com/quartiq/phaser","commit_stats":null,"previous_names":[],"tags_count":6,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/quartiq%2Fphaser","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/quartiq%2Fphaser/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/quartiq%2Fphaser/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/quartiq%2Fphaser/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/quartiq","download_url":"https://codeload.github.com/quartiq/phaser/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253160764,"owners_count":21863627,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-09T12:09:18.859Z","updated_at":"2025-05-08T23:01:43.469Z","avatar_url":"https://github.com/quartiq.png","language":"Jupyter Notebook","readme":"[![QUARTIQ Matrix Chat](https://img.shields.io/matrix/quartiq:matrix.org)](https://matrix.to/#/#quartiq:matrix.org)\n\n# Phaser gateware\n\nThis repository contains the gateware for the Phaser 4 channel 1 GS/s DAC arbitrary waveform generator.\n\nFunded by [Oxford](https://github.com/OxfordIonTrapGroup), [Oregon](https://github.com/OregonIons), [MITLL](https://www.ll.mit.edu/biographies/jeremy-m-sage), [QUARTIQ](https://github.com/quartiq).\n\nThis software is licenses under the GNU General Public License version 3 (GPL-3) or\nlater.\n\n## Hardware\n\nThe hardware design repository is over at [Sinara](https://github.com/sinara-hw/Phaser).\n\n## DSP designs\n\n[NBViewer link](https://nbviewer.jupyter.org/github/quartiq/phaser/tree/master/)\n\n* [filter](https://nbviewer.jupyter.org/github/quartiq/phaser/blob/master/filter.ipynb):\n  ideas and sketches for a 1/10 (samples per clock cycle) to 2/1 interpolator\n  cascade, analysis of other interpolator approaches, comparison of\n  CIC/HBF/FIR, CIC droop compensation filter\n* [cic](https://nbviewer.jupyter.org/github/quartiq/phaser/blob/master/cic.ipynb): ideas for CIC implementations and tests of interpolation modes\n\n## Getting started\n\n### Loading bitstreams\n\nPrecompiled bitstreams are available under [releases](https://github.com/quartiq/phaser/releases).\n\nWith vivado and a vivado-compatible JTAG dongle, to load (volatile) a bitstream onto the FPGA, use:\n\n`vivado -mode batch -source load.tcl -tclargs build/phaser.bit`\n\nTo flash it, use:\n\n`vivado -mode batch -source flash.tcl -tclargs build/phaser.bit`\n\nWith openocd and a JTAG dongle that fits the connector and has openocd support it\nshould also be possible to load and flash using the `xc7a` support and the `jtagspi` proxy bitstreams.\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fquartiq%2Fphaser","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fquartiq%2Fphaser","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fquartiq%2Fphaser/lists"}