{"id":16215770,"url":"https://github.com/rainingcomputers/srp16","last_synced_at":"2025-04-07T22:42:04.358Z","repository":{"id":102305493,"uuid":"202963087","full_name":"RainingComputers/SRP16","owner":"RainingComputers","description":"SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.","archived":false,"fork":false,"pushed_at":"2021-10-17T04:06:47.000Z","size":22938,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-02-14T00:14:13.423Z","etag":null,"topics":["cpu","instruction-set-architecture","isa","isa-specification","microcontrollers","open-embedded","open-isa","risc","soft-core","verilog"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/RainingComputers.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-08-18T05:20:02.000Z","updated_at":"2021-10-17T04:06:50.000Z","dependencies_parsed_at":null,"dependency_job_id":"b3dd62fc-9213-4d0a-afe9-42b512560829","html_url":"https://github.com/RainingComputers/SRP16","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RainingComputers%2FSRP16","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RainingComputers%2FSRP16/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RainingComputers%2FSRP16/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RainingComputers%2FSRP16/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/RainingComputers","download_url":"https://codeload.github.com/RainingComputers/SRP16/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247744284,"owners_count":20988781,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","instruction-set-architecture","isa","isa-specification","microcontrollers","open-embedded","open-isa","risc","soft-core","verilog"],"created_at":"2024-10-10T11:16:21.619Z","updated_at":"2025-04-07T22:42:04.334Z","avatar_url":"https://github.com/RainingComputers.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"## SRP16\nSRP16 is free and open ISA for 16-bit CPUs and Microcontrollers. \n\n## Project Status\n### Specification\n+ SRP16 ISA Specifaction [[.pdf]](Documentation/SRP16%20ISA%20Specification.pdf)\n+ SRP16 Assembler Guide [[.pdf]](Documentation/SRP16%20Assembler%20Guide.pdf)\n+ SRP16 ISA Simulator Manual [[.pdf]](Documentation/ISA%20Simulator%20Manual.pdf)\n+ .dhex File Specification [[.pdf]](Documentation/dhex%20Specification.pdf)\n\n### Roadmap\n- [x] ISA Specification\n- [x] Reference Implementation in Icarus Verilog\n- [ ] Reference Implementation in Lattice iCEstick\n- [x] Assembler\n- [x] ISA Simulator\n- [ ] I/O, Interrupts and Timers\n\n## ISA Quick Reference\n### Registers:\n+ General Purpose Registers R0-R15 (Accessible by Load-Store Instructions)\n+ General Purpose Registers R16-R31 (Not Accessible by Load-Store Instructions)\n+ Accumulator Register (R60)\n+ Memory Pointer Register or MPTR (R61)\n+ Stack Pointer or SP (R62)\n+ Program Counter or PC (R63)\n+ POP, PUSH, INC, DEC instructions can only access General Purpose Registers R0-R31\n\n### Instructions:\n| Instruction                       | Operation\t\t\t\t\t\t\t\t\t\t\t|\n| --------------------------------- | ------------------------------------------------- |\n| LDR Rx, 8-bit-signed-immediate    | Rx ⟵ immediate\t\t\t\t\t\t\t\t\t|\n| LDRU Rx, 8-bit-unsigned-immediate | Rx[15:8] ⟵ immediate\t\t\t\t\t\t\t\t|\n| LD@MPTR Rx, 8-bit-signed-offset   | Rx ⟵ memory[MPTR]\t\u003cbr\u003e MPTR ⟵ MPTR+offset\t\t\t|\n| ST@MPTR Rx, 8-bit-signed-offset   | memory[MPTR] ⟵ Rx\t\u003cbr\u003e MPTR ⟵ MPTR+offset\t\t\t|\n| LDB@MPTR Rx, 8-bit-signed-offset  | Rx[7:0] ⟵ memory[MPTR] \u003cbr\u003e MPTR ⟵ MPTR+offset\t|\n| STB@MPTR Rx, 8-bit-signed-offset  | memory[MPTR] ⟵ Rx[7:0] \u003cbr\u003e MPTR ⟵ MPTR+offset\t|\n| LDA 12-bit-signed-immediate       | A ⟵ immediate\t\t\t\t\t\t\t\t\t\t|\n| LDAU 6-bit-unsigned-immediate     | A[15:12] ⟵ immediate[3:0]\t\t\t\t\t\t\t|\n| LDMPTR 12-bit-unsigned-immediate  | MPTR ⟵ immediate\t\t\t\t\t\t\t\t\t|\n| LDMPTRU 12-bit-signed-immediate   | MPTR[15:12] ⟵ immediate[3:0]\t\t\t\t\t\t|\n| MOV Rx, Ry                        | Rx ⟵ Ry\t\t\t\t\t\t\t\t\t\t\t|\n| MOV Rx, PC                        | Rx ⟵ PC+4\t\t\t\t\t\t\t\t\t\t\t|\n| JMP Ry or MOV PC, Ry              | PC ⟵ Ry\t\t\t\t\t\t\t\t\t\t\t|\n| SJMP 12-bit-signed-offset         | PC ⟵ PC+offset\t\t\t\t\t\t\t\t\t|\n| SJMPF 12-bit-signed-offset        | if(flag): PC ⟵ PC+offset\t\t\t\t\t\t\t|\n| NOTF                              | flag ⟵ !flag\t\t\t\t\t\t\t\t\t\t|\n| POP Rx                            | Rx ⟵ memory[SP] \u003cbr\u003e SP ⟵ SP+1\t\t\t\t\t|\n| PUSH Rx                           | SP ⟵ SP-1\t\u003cbr\u003e memory[SP] ⟵ Rx\t\t\t\t\t|\n| INC Rx                            | Rx ⟵ Rx+1\t\t\t\t\t\t\t\t\t\t\t|\n| DEC Rx                            | Rx ⟵ Rx-1\t\t\t\t\t\t\t\t\t\t\t|\n| ADDI 8-bit-signed-immediate       | A ⟵ A+immediate\t\t\t\t\t\t\t\t\t|\n| ADCI 8-bit-signed-immediate       | A ⟵ A+immediate+carry\t\t\t\t\t\t\t\t|\n| SBBI 8-bit-signed-immediate       | A ⟵ A-immediate-carry\t\t\t\t\t\t\t\t|\n| ANDI 8-bit-signed-immediate       | A ⟵ A\u0026immediate\t\t\t\t\t\t\t\t\t|\n| ORI 8-bit-signed-immediate        | A ⟵ A|immediate\t\t\t\t\t\t\t\t\t|\n| XORI 8-bit-signed-immediate       | A ⟵ A^immediate\t\t\t\t\t\t\t\t\t|\n| SLAI 6-bit-unsigned-immediate     | A ⟵ A\u003c\u003c\u003cimmediate\t\t\t\t\t\t\t\t\t|\n| SRAI 6-bit-unsigned-immediate     | A ⟵ A\u003e\u003e\u003eimmediate\t\t\t\t\t\t\t\t\t|\n| SLLI 6-bit-unsigned-immediate     | A ⟵ A\u003c\u003cimmediate\t\t\t\t\t\t\t\t\t|\n| SRLI 6-bit-unsigned-immediate     | A ⟵ A\u003e\u003eimmediate\t\t\t\t\t\t\t\t\t|\n| ADD Rx                            | A ⟵ A+Rx\t\t\t\t\t\t\t\t\t\t\t|\n| SUB Rx                            | A ⟵ A-Rx\t\t\t\t\t\t\t\t\t\t\t|\n| ADC Rx                            | A ⟵ A+Rx+carry\t\t\t\t\t\t\t\t\t|\n| SBB Rx                            | A ⟵ A-Rx-carry\t\t\t\t\t\t\t\t\t|\n| AND Rx                            | A ⟵ A\u0026Rx\t\t\t\t\t\t\t\t\t\t\t|\t\t\t\n| OR Rx                             | A ⟵ A|Rx\t\t\t\t\t\t\t\t\t\t\t|\t\t\t\n| XOR Rx                            | A ⟵ A^Rx\t\t\t\t\t\t\t\t\t\t\t|\t\t\t\n| SLA Rx                            | A ⟵ A\u003c\u003c\u003cRx\t\t\t\t\t\t\t\t\t\t|\t\t\t\n| SRA Rx                            | A ⟵ A\u003e\u003e\u003eRx\t\t\t\t\t\t\t\t\t\t|\t\t\t\n| SLL Rx                            | A ⟵ A\u003c\u003cRx\t\t\t\t\t\t\t\t\t\t\t|\n| SRL Rx                            | A ⟵ A\u003e\u003eRx\t\t\t\t\t\t\t\t\t\t\t|\n| CLI 8-bit-signed-immediate        | if(A\u003cimmediate): flag ⟵ 1 \u003cbr\u003e else: flag ⟵ 0\t\t|\n| CGI 8-bit-signed-immediate        | if(A\u003eimmediate): flag ⟵ 1 \u003cbr\u003e else: flag ⟵ 0\t\t|\n| CEI 8-bit-signed-immediate        | if(A==immediate): flag ⟵ 1 \u003cbr\u003e else: flag ⟵ 0\t|\n| CL Rx                             | if(A\u003cRx): flag ⟵ 1 \u003cbr\u003e else: flag ⟵ 0\t\t\t|\n| CG Rx                             | if(A\u003eRx): flag ⟵ 1 \u003cbr\u003e else: flag ⟵ 0\t\t\t|\n| CE Rx                             | if(A==Rx): flag ⟵ 1 \u003cbr\u003e else: flag ⟵ 0\t\t\t|\n\n## Installing toolchain\n+ Clone repo, `cd` into it\n```\ngit clone https://github.com/RainingComputers/SRP16.git\ncd SRP16\n```\n+ Install readline library\n```\nsudo apt-get install libreadline-dev\n```\n+ Compile and build executable,\n```\nmake build\n```\n+ Install, requires root privilege\n```\nsudo make install\n```\n\n## Getting started\nLet's write a simple program to generate fibonacci numbers, and save it as `test.asm`\n```\n\tlda 1\t\t\t\t\t\n\tldr r0, 0\t\t;Load initial values\t\t\n\tldr r1, 1\t\t\t\t\nloop:\t\t\t\t\t\t\n\tadd r0\t\t\t\t\t\n\tmov r0, r1\t\t\t\n\tmov r1, a\t\t;Add to accumulator\t\t\n\tsjmp loop\t\t;Loop\n```\nNow to assemble the program, \n```\nsrp16asm test.asm -s test.dhex\n```\nNow, to start the simulator,\n```\nsrp16sim test.dhex\n```\nYou will see a prompt,\n```\n(pc@0x0000) █  \n```\nLet's set a break point at end of the loop,\n```\n(pc@0x0000) bp \"test.asm\" 8\n```\nNow use `run` command to run it, and `a` to view contents of the accumulator,\n```\n(pc@0x0000) run\n(pc@0x000c) a\na = 0x0001\n(pc@0x000c) run\n(pc@0x000c) a\na = 0x0002\n(pc@0x000c) run\n(pc@0x000c) a\na = 0x0003\n(pc@0x000c) run\n(pc@0x000c) a\na = 0x0005\n```\n\n## License\n+ MIT License. See: https://github.com/RainingComputers/SRP16/blob/master/LICENSE.md\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frainingcomputers%2Fsrp16","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frainingcomputers%2Fsrp16","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frainingcomputers%2Fsrp16/lists"}