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Digital Logic Exercises Using FPGAs* by Kurt Wick.\n\n# Setup\n\nThe toolchain used for this project is Vivado 2018.1 -- you can download the free (Webpack) version here: https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html\n\n# Installation\n\nEach project folder contains a bitfile (.bit) which you can directly program onto compatible Xilinx FPGAs.\n\nFor development, I used a [Digilent Basys3 ](https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/) development board, but the examples are generally hardware-agnostic as long as you provide your own constraints file and your board has the required hardware components:\n\n* A seven-segment display\n* DIP switches\n* A USB interface\n* At least one available PMOD connector\n\nAdditionally, some of the other examples require external hardware components like:\n\n* External flash\n* External audio amplifier\n\n# Table of contents\n\n## Chapter 3\n\n* Half-adder\n* Full-adder \n* 8-bit adder\n\n## Chapter 4\n* 4-bit ripple counter\n* A 44.1 KHz audio \"clock\"\n* A PWM Audio player\n\n## Chapter 5\n\n* FSM frequency counter\n* FSM frequency counter, that uses a soft-core processor and communicates with PC via UART.","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fraleighlittles%2Fapplied_digital_logic_exercises_using_fpgas","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fraleighlittles%2Fapplied_digital_logic_exercises_using_fpgas","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fraleighlittles%2Fapplied_digital_logic_exercises_using_fpgas/lists"}