{"id":21861566,"url":"https://github.com/raleighlittles/basys3countdownclock","last_synced_at":"2026-01-03T23:49:54.273Z","repository":{"id":117726086,"uuid":"171221731","full_name":"raleighlittles/Basys3CountdownClock","owner":"raleighlittles","description":"Extremely basic countdown clock project for the Basys 3 FPGA development board.","archived":false,"fork":false,"pushed_at":"2019-02-18T05:53:00.000Z","size":6,"stargazers_count":4,"open_issues_count":0,"forks_count":1,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-01-26T14:52:42.369Z","etag":null,"topics":["basys-3","basys3","fpga","hdl","seven-segment-display","verilog","vivado","xdc","xilinx"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/raleighlittles.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-02-18T05:41:40.000Z","updated_at":"2024-12-24T11:34:25.000Z","dependencies_parsed_at":null,"dependency_job_id":"1478f177-bb46-4703-b270-2a1f88451d7d","html_url":"https://github.com/raleighlittles/Basys3CountdownClock","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/raleighlittles%2FBasys3CountdownClock","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/raleighlittles%2FBasys3CountdownClock/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/raleighlittles%2FBasys3CountdownClock/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/raleighlittles%2FBasys3CountdownClock/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/raleighlittles","download_url":"https://codeload.github.com/raleighlittles/Basys3CountdownClock/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":244860600,"owners_count":20522466,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["basys-3","basys3","fpga","hdl","seven-segment-display","verilog","vivado","xdc","xilinx"],"created_at":"2024-11-28T03:11:59.329Z","updated_at":"2026-01-03T23:49:54.239Z","avatar_url":"https://github.com/raleighlittles.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# About\n\n*Very* basic implementation of a countdown clock, written for the [Basys 3 FPGA trainer board](https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/).\n\nUses the 4 7-segment displays available to start counting down from 9999 to 0 and then back to 9999 again.\n\n# Setup\n\n## Pre-requisites\n\n* [Vivado Design Suite](https://www.xilinx.com/products/design-tools/vivado.html) \n\n## Instructions\n\n* Import source and constraints file\n* Run Synthesis\n* Run Implementation\n* Generate bitstream\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fraleighlittles%2Fbasys3countdownclock","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fraleighlittles%2Fbasys3countdownclock","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fraleighlittles%2Fbasys3countdownclock/lists"}