{"id":17160360,"url":"https://github.com/rauhul/ece385","last_synced_at":"2026-03-18T23:44:16.032Z","repository":{"id":75866183,"uuid":"82992671","full_name":"rauhul/ece385","owner":"rauhul","description":"Digital Systems Laboratory UIUC FA 2016","archived":false,"fork":false,"pushed_at":"2017-02-24T02:35:52.000Z","size":58236,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"master","last_synced_at":"2025-08-03T10:38:29.471Z","etag":null,"topics":["altera","fpga","quartus-prime","systemverilog","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rauhul.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2017-02-24T02:28:45.000Z","updated_at":"2025-04-12T02:52:01.000Z","dependencies_parsed_at":null,"dependency_job_id":"483274c5-f7de-4608-9ca5-8be9e8e98c53","html_url":"https://github.com/rauhul/ece385","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/rauhul/ece385","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rauhul%2Fece385","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rauhul%2Fece385/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rauhul%2Fece385/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rauhul%2Fece385/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rauhul","download_url":"https://codeload.github.com/rauhul/ece385/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rauhul%2Fece385/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":279006098,"owners_count":26084026,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-10-11T02:00:06.511Z","response_time":55,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["altera","fpga","quartus-prime","systemverilog","verilog"],"created_at":"2024-10-14T22:24:37.928Z","updated_at":"2025-10-11T03:18:49.223Z","avatar_url":"https://github.com/rauhul.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# ece385\nDigital Systems Laboratory UIUC FA 2017\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frauhul%2Fece385","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frauhul%2Fece385","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frauhul%2Fece385/lists"}