{"id":30821275,"url":"https://github.com/ravi-prakash1907/computer-system-architecture","last_synced_at":"2025-09-06T10:48:38.701Z","repository":{"id":47009820,"uuid":"204417450","full_name":"ravi-prakash1907/Computer-System-Architecture","owner":"ravi-prakash1907","description":"A B.Sc. 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[Sample Machines](https://github.com/ravi-prakash1907/Computer-System-Architecture/tree/master/Machines)  \r\n\u003e   - For [Diret Instruction-Set](https://github.com/ravi-prakash1907/Computer-System-Architecture/tree/master/Machines/2061_Direct_Ravi)  \r\n\u003e   - For [Indiret Instruction-Set](https://github.com/ravi-prakash1907/Computer-System-Architecture/tree/master/Machines/2061_Indirect_Ravi)  \r\n\u003e 2. [Solutions to the Practicle Programs](https://github.com/ravi-prakash1907/Computer-System-Architecture/tree/master/Operations%20for%20Programs)  \r\n\u003e 3. [Download _CPUSim 3.6.9_](https://github.com/ravi-prakash1907/Computer-System-Architecture/raw/master/CPUSim3.6.9%20Downloadable.tar.gz)  \r\n\u003e 4. [CPUSim Official](https://www.cs.colby.edu/djskrien/CPUSim/)  \r\n\u003e \r\n\r\n---  \r\n\r\n## Practical List  \r\n![P1](./Practical%20List/p1.png)\r\n![P2](./Practical%20List/p2.png)\r\n\r\n\r\n## The Header:\r\n  { **[OP-Code] [---ADDR---]** }\r\n\r\n  OP-Code: It's operation code of the instruction which is of 4-bits usually\r\n  ADDR: It's the address field where the actual data is stored \u0026 has a size of 12-bits\r\n\r\n\r\n## Registers in CPU:\r\n```\r\n\r\n1. AC  \r\n   Accumulator Counter  \r\n   16-bits  \r\n   Mainly used for final computation  \r\n\r\n2. PC  \r\n   Program Counter  \r\n   12-bits  \r\n   Used to store of next step i.e. to be executed  \r\n\r\n3. IR  \r\n   Information Register  \r\n   16-bits  \r\n   Keeps **entire** data instructions  \r\n\r\n4. DR  \r\n   Data Register  \r\n   16-bits  \r\n   It stores actual data (_eg. y = 10_)  \r\n\r\n5. AR  \r\n   Address Register  \r\n   12-bits  \r\n   The address is stored here  \r\n\r\n6. I  \r\n   Index  \r\n   1-bit  \r\n   Stores the **index** of value/data  \r\n\r\n7. S  \r\n   Switch i.e. flip-flop  \r\n   1-bit  \r\n   Stores instruction about Start/Stop flip-flop  \r\n\r\n8. E  \r\n   Extra  \r\n   1-bit  \r\n   It stores the carry-bit (_eg. while adding 1+1, E will store '1'_)  \r\n\r\n```  \r\n\r\n---  \r\n\r\n## Instruction cycle for the execution of any program:\r\n\r\na. **Fetch**:\r\n    _An instruction if fetched from the memory_\r\n\r\nb. **Decode**:\r\n    _Decodes the fetched instruction_\r\n\r\nc. **Read**:\r\n    _The effective i.e. actual address is extracted from the memory_  \r\n    _It's an instruction that has an Indirect address_  \r\n\r\nd. **Execution**:\r\n    _Finally the fetched instruction is executed_\r\n\r\n\r\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fravi-prakash1907%2Fcomputer-system-architecture","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fravi-prakash1907%2Fcomputer-system-architecture","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fravi-prakash1907%2Fcomputer-system-architecture/lists"}