{"id":23140874,"url":"https://github.com/raycar5/logicsim","last_synced_at":"2025-08-17T13:31:34.641Z","repository":{"id":62442448,"uuid":"314060169","full_name":"raycar5/logicsim","owner":"raycar5","description":"Composable digital logic simulation in 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alt=\"github\" src=\"https://img.shields.io/badge/github-raycar5/logicsim-8da0cb?style=for-the-badge\u0026labelColor=555555\u0026logo=github\" height=\"20\"\u003e](https://github.com/raycar5/logicsim)\n[\u003cimg alt=\"crates.io\" src=\"https://img.shields.io/crates/v/logicsim.svg?style=for-the-badge\u0026color=fc8d62\u0026logo=rust\" height=\"20\"\u003e](https://crates.io/crates/logicsim)\n[\u003cimg alt=\"docs.rs\" src=\"https://img.shields.io/badge/docs.rs-logicsim-66c2a5?style=for-the-badge\u0026labelColor=555555\u0026logoColor=white\u0026logo=data:image/svg+xml;base64,PHN2ZyByb2xlPSJpbWciIHhtbG5zPSJodHRwOi8vd3d3LnczLm9yZy8yMDAwL3N2ZyIgdmlld0JveD0iMCAwIDUxMiA1MTIiPjxwYXRoIGZpbGw9IiNmNWY1ZjUiIGQ9Ik00ODguNiAyNTAuMkwzOTIgMjE0VjEwNS41YzAtMTUtOS4zLTI4LjQtMjMuNC0zMy43bC0xMDAtMzcuNWMtOC4xLTMuMS0xNy4xLTMuMS0yNS4zIDBsLTEwMCAzNy41Yy0xNC4xIDUuMy0yMy40IDE4LjctMjMuNCAzMy43VjIxNGwtOTYuNiAzNi4yQzkuMyAyNTUuNSAwIDI2OC45IDAgMjgzLjlWMzk0YzAgMTMuNiA3LjcgMjYuMSAxOS45IDMyLjJsMTAwIDUwYzEwLjEgNS4xIDIyLjEgNS4xIDMyLjIgMGwxMDMuOS01MiAxMDMuOSA1MmMxMC4xIDUuMSAyMi4xIDUuMSAzMi4yIDBsMTAwLTUwYzEyLjItNi4xIDE5LjktMTguNiAxOS45LTMyLjJWMjgzLjljMC0xNS05LjMtMjguNC0yMy40LTMzLjd6TTM1OCAyMTQuOGwtODUgMzEuOXYtNjguMmw4NS0zN3Y3My4zek0xNTQgMTA0LjFsMTAyLTM4LjIgMTAyIDM4LjJ2LjZsLTEwMiA0MS40LTEwMi00MS40di0uNnptODQgMjkxLjFsLTg1IDQyLjV2LTc5LjFsODUtMzguOHY3NS40em0wLTExMmwtMTAyIDQxLjQtMTAyLTQxLjR2LS42bDEwMi0zOC4yIDEwMiAzOC4ydi42em0yNDAgMTEybC04NSA0Mi41di03OS4xbDg1LTM4Ljh2NzUuNHptMC0xMTJsLTEwMiA0MS40LTEwMi00MS40di0uNmwxMDItMzguMiAxMDIgMzguMnYuNnoiPjwvcGF0aD48L3N2Zz4K\" height=\"20\"\u003e](https://docs.rs/logicsim)\n[\u003cimg alt=\"build status\" src=\"https://img.shields.io/github/workflow/status/raycar5/logicsim/Rust/master?style=for-the-badge\" height=\"20\"\u003e](https://github.com/raycar5/logicsim/actions?query=branch%3Amaster)\n\n# logicsim\n\nCreate and simulate digital circuits with Rust abstractions!\n\nIn logicsim you use a [GateGraphBuilder][GateGraphBuilder] to create and connect logic gates,\nconceptually the logic gates are represented as nodes in a graph with dependency edges to other nodes.\n\nInputs are represented by constants([ON][ON], [OFF][OFF]) and [levers][lever].\n\nOutputs are represented by [OutputHandles][OutputHandle] which allow you to query the state of gates and\nare created by calling [GateGraphBuilder::output][output].\n\nOnce the graph is initialized, it transforms into an [InitializedGateGraph][InitializedGateGraph] which cannot be modified.\nThe initialization process optimizes the gate graph so that expressive abstractions\nthat potentially generate lots of constants or useless gates can be used without fear.\nAll constants and dead gates will be optimized away and the remaining graph simplified very aggressively.\n\n**Zero overhead abstractions!**\n\n## Examples\nSimple gates.\n```rust\nlet mut g = GateGraphBuilder::new();\n\n// Providing each gate with a string name allows for great debugging.\n// If you don't want them affecting performance, you can disable\n// feature \"debug_gates\" and all of the strings will be optimized away.\nlet or = g.or2(ON, OFF, \"or\");\nlet or_output = g.output1(or, \"or_output\");\n\nlet and = g.and2(ON, OFF, \"and\");\nlet and_output = g.output1(and, \"and_output\");\n\nlet ig = \u0026g.init();\n\n// `b0()` accesses the 0th bit of the output.\n// Outputs can have as many bits as you want\n// and be accessed with methods like `u8()`, `char()` or `i128()`.\nassert_eq!(or_output.b0(ig), true);\nassert_eq!(and_output.b0(ig), false);\n```\n\nLevers!\n```rust\nlet l1 = g.lever(\"l1\");\nlet l2 = g.lever(\"l2\");\n\nlet or = g.or2(l1.bit(), l2.bit(), \"or\");\nlet or_output = g.output1(or, \"or_output\");\n\nlet and = g.and2(l1.bit(), l2.bit(), \"and\");\nlet and_output = g.output1(and, \"and_output\");\n\nlet ig = \u0026mut g.init();\n\nassert_eq!(or_output.b0(ig), false);\nassert_eq!(and_output.b0(ig), false);\n\n// `_stable` means that the graph will run until gate states\n//  have stopped changing. This might not be what you want\n// if you have a circuit that never stabilizes like 3 not gates\n// connected in a loop!\n// See [InitializedGateGraph::run_until_stable].\nig.flip_lever_stable(l1);\nassert_eq!(or_output.b0(ig), true);\nassert_eq!(and_output.b0(ig), false);\n\nig.flip_lever_stable(l2);\nassert_eq!(or_output.b0(ig), true);\nassert_eq!(and_output.b0(ig), true);\n```\n\n[SR Latch!](https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_NOR_latch)\n```rust\nlet r = g.lever(\"l1\");\nlet s = g.lever(\"l2\");\n\nlet q = g.nor2(r.bit(), OFF, \"q\");\nlet nq = g.nor2(s.bit(), q, \"nq\");\n\nlet q_output = g.output1(q, \"q\");\nlet nq_output = g.output1(nq, \"nq\");\n\n// `d1()` replaces the dependency at index 1 with nq.\n// We used OFF as a placeholder above.\ng.d1(q, nq);\n\nlet ig = \u0026mut g.init();\n// With latches, the initial state should be treated as undefined,\n// so remember to always reset your latches at the beginning\n// of the simulation.\nig.pulse_lever_stable(r);\nassert_eq!(q_output.b0(ig), false);\nassert_eq!(nq_output.b0(ig), true);\n\nig.pulse_lever_stable(s);\nassert_eq!(q_output.b0(ig), true);\nassert_eq!(nq_output.b0(ig), false);\n\nig.pulse_lever_stable(r);\nassert_eq!(q_output.b0(ig), false);\nassert_eq!(nq_output.b0(ig), true);\n```\n\n## The 8 bit computer\n\nIn the examples folder you'll find a very simple 8 bit computer, it's a great showcase of what you can achieve by using Rust's constructs\nto create modular circuit abstractions.\n\nYou can play with it in only 3 shell commands! ([Assuming you have cargo installed](https://rustup.rs/)).\n```sh\ngit clone https://github.com/raycar5/logicsim\ncd logicsim\ncargo run --release --example computer greeter\n```\n\n## Built in circuits\n\nThe `circuits` module features a lot of useful pre-built generic components like:\n\n- [WordInput][WordInput]\n- [Bus][Bus]\n- [Wire][Wire]\n- [d_flip_flop][d_flip_flop]\n- [rom][rom]\n\n[and many more!][circuits]\n\n## Debugging\n\nCurrently there are 2 debugging tools:\n\n### Probes\n\nCalling [GateGraphBuilder::probe][probe] allows you to create probes, which will print the value of all of the bits provided\nalong with their name whenever any of the bits change state within a [tick][tick].\n\n### Example:\n```rust\nlet mut g = GateGraphBuilder::new();\n\nlet l1 = g.lever(\"l1\");\nlet l2 = g.lever(\"l2\");\n\n\nlet or = g.xor2(l1.bit(), l2.bit(), \"or\");\nlet xor = g.xor2(l1.bit(), l2.bit(), \"xor\");\ng.probe(\u0026[or,xor],\"or_xor\");\nlet xor_output = g.output1(xor, \"xor_output\");\n\n\nlet ig = \u0026mut g.init();\nassert_eq!(xor_output.b0(ig), false);\n\nig.set_lever_stable(l1);\nassert_eq!(xor_output.b0(ig), true);\n\nig.set_lever_stable(l2);\nassert_eq!(xor_output.b0(ig), false);\n\nig.reset_lever_stable(l1);\nassert_eq!(xor_output.b0(ig), true);\n\nig.reset_lever_stable(l2);\nassert_eq!(xor_output.b0(ig), false);\n```\nIn the terminal you'll see:\n```sh\nor_xor: 3\nor_xor: 1\nor_xor: 3\nor_xor: 0\n```\n\n### .dot files\n\nUsing the method [InitializedGateGraph::dump_dot][dump_dot] you can generate [.dot](https://en.wikipedia.org/wiki/DOT_(graph_description_language))\nfiles which can be viewed in many different graph viewers. I recommend [gephi](https://gephi.org/), many others can't handle the size of the graphs\ngenerated by logicsim.\n\nFor example here is the graph representation of the [8 bit computer](#the-8-bit-computer):\n\n\u003cimg src=\"https://i.imgur.com/kOiiAKa.png\" width=\"400px\" height=\"271px\"\u003e\n\nIf we zoom in a bit we can see each node is labeled with its name which can help debug really weird bugs.\n\n\u003cimg src=\"https://i.imgur.com/4Y5SOx0.png\" width=\"400px\" height=\"271px\"\u003e\n\n## Next steps\n\n- Better debugging: I want a gui where I can see many outputs at once with logic-analyzer-like features, probably web based.\n- More thorough optimization testing and documentation: I have documented and tested a lot of the public API surface but the optimizations folder\nneeds some love.\n- RISC-V: I want to test out the limits of logicsim by implementing a RISC-V core and running Rust programs in it!\n- Compiling: Right now logicsim is just an interpreter, I might try making it compile circuits to either Rust or x86_64 directly.\n- Synthesizing: I have a nice fpga dev kit next to me and it would be pretty cool if I could synthesize circuits built in logicsim into it.\n\n[GateGraphBuilder]: https://docs.rs/logicsim/0.1.7/logicsim/graph/struct.GateGraphBuilder.html\n[ON]: https://docs.rs/logicsim/0.1.7/logicsim/graph/constant.ON.html\n[OFF]: https://docs.rs/logicsim/0.1.7/logicsim/graph/constant.OFF.html\n[lever]: https://docs.rs/logicsim/0.1.7/logicsim/graph/struct.GateGraphBuilder.html#method.lever\n[OutputHandle]: https://docs.rs/logicsim/0.1.7/logicsim/graph/struct.OutputHandle.html\n[output]: https://docs.rs/logicsim/0.1.7/logicsim/graph/struct.GateGraphBuilder.html#method.output\n[InitializedGateGraph]: https://docs.rs/logicsim/0.1.7/logicsim/graph/struct.InitializedGateGraph.html\n[WordInput]: https://docs.rs/logicsim/0.1.7/logicsim/circuits/struct.WordInput.html\n[Bus]: https://docs.rs/logicsim/0.1.7/logicsim/circuits/struct.Bus.html\n[Wire]: https://docs.rs/logicsim/0.1.7/logicsim/circuits/struct.Wire.html\n[d_flip_flop]: https://docs.rs/logicsim/0.1.7/logicsim/circuits/fn.d_flip_flop.html\n[rom]: https://docs.rs/logicsim/0.1.7/logicsim/circuits/fn.rom.html\n[circuits]: https://docs.rs/logicsim/0.1.7/logicsim/circuits/index.html\n[probe]: https://docs.rs/logicsim/0.1.7/logicsim/graph/struct.GateGraphBuilder.html#method.probe\n[tick]: https://docs.rs/logicsim/0.1.7/logicsim/graph/struct.InitializedGateGraph.html#method.tick\n[dump_dot]: https://docs.rs/logicsim/0.1.7/logicsim/graph/struct.InitializedGateGraph.html#method.dump_dot\n\n\n## License: MIT\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fraycar5%2Flogicsim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fraycar5%2Flogicsim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fraycar5%2Flogicsim/lists"}