{"id":16833254,"url":"https://github.com/rejunity/atari-2600-fpga","last_synced_at":"2026-01-04T03:43:01.615Z","repository":{"id":139192255,"uuid":"432225536","full_name":"rejunity/Atari-2600-FPGA","owner":"rejunity","description":"Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.","archived":false,"fork":false,"pushed_at":"2021-11-28T11:30:27.000Z","size":110,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":3,"default_branch":"main","last_synced_at":"2025-03-15T15:54:35.327Z","etag":null,"topics":["atari-2600","atari2600","fpga","retrogaming","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rejunity.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-11-26T15:35:32.000Z","updated_at":"2021-11-28T11:30:29.000Z","dependencies_parsed_at":null,"dependency_job_id":"91fddaed-c4b1-45d9-9d0b-ef32b9d474b6","html_url":"https://github.com/rejunity/Atari-2600-FPGA","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2FAtari-2600-FPGA","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2FAtari-2600-FPGA/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2FAtari-2600-FPGA/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2FAtari-2600-FPGA/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rejunity","download_url":"https://codeload.github.com/rejunity/Atari-2600-FPGA/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":244135905,"owners_count":20403797,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["atari-2600","atari2600","fpga","retrogaming","verilog"],"created_at":"2024-10-13T11:52:52.389Z","updated_at":"2026-01-04T03:43:01.575Z","avatar_url":"https://github.com/rejunity.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Atari-2600\nAtari 2600 in Verilog.\n\nBased on the Daniel Beer's earlier work [\"Atari on an FPGA\"](https://people.ece.cornell.edu/land/courses/eceprojectsland/STUDENTPROJ/2006to2007/dbb26/dbb28_meng_report.pdf).\n\n## Plan\n\n1. Replace CPU 6502 VHDL implementation with Verilog.\n    - [ ] Integrate Andrew Holme [Verilog 6502](http://www.aholme.co.uk/6502/Main.htm) core\n    - [ ] Integrate Arlet Ottens [Verilog 6502](https://github.com/Arlet/verilog-6502) core\n- Minimize vendor dependent code, move it out of the main files.\n    - [ ] Remove PLL from mySystem.v\n    - [ ] Separate folder for IceBreaker and Altera specific code\n- Make codebase compatible with the open-source tools: [iverilog](http://iverilog.icarus.com/), [yosys](https://github.com/YosysHQ/yosys).\n    - [ ] Makefile\n- Testbench, coco_tb, compare to python emu\n- Try to fit on open-source [iCEBreaker FPGA](https://www.crowdsupply.com/1bitsquared/icebreaker-fpga) (Lattice iCE40UP5k).\n- [ASIC](https://www.zerotoasiccourse.com/)! :)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frejunity%2Fatari-2600-fpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frejunity%2Fatari-2600-fpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frejunity%2Fatari-2600-fpga/lists"}