{"id":16833258,"url":"https://github.com/rejunity/tt05-rule110","last_synced_at":"2026-02-16T13:03:41.946Z","repository":{"id":193872710,"uuid":"689596867","full_name":"rejunity/tt05-rule110","owner":"rejunity","description":" Rule110 Cellular Automata ASIC for Tiny Tapeout 05","archived":false,"fork":false,"pushed_at":"2023-11-09T08:39:12.000Z","size":4171,"stargazers_count":5,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-10-08T02:59:46.299Z","etag":null,"topics":["asic","cellular-automata","cellular-automaton","pseudo-random-generator","rule110","tapeout"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rejunity.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-09-10T10:20:31.000Z","updated_at":"2025-02-14T16:07:48.000Z","dependencies_parsed_at":"2024-11-24T06:11:42.919Z","dependency_job_id":"0fd888a7-5905-4105-aa0e-28bd65e05d8c","html_url":"https://github.com/rejunity/tt05-rule110","commit_stats":null,"previous_names":["rejunity/tt05-rule110"],"tags_count":0,"template":false,"template_full_name":"TinyTapeout/tt05-submission-template","purl":"pkg:github/rejunity/tt05-rule110","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2Ftt05-rule110","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2Ftt05-rule110/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2Ftt05-rule110/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2Ftt05-rule110/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rejunity","download_url":"https://codeload.github.com/rejunity/tt05-rule110/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2Ftt05-rule110/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29508740,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-16T09:05:14.864Z","status":"ssl_error","status_checked_at":"2026-02-16T08:55:59.364Z","response_time":115,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","cellular-automata","cellular-automaton","pseudo-random-generator","rule110","tapeout"],"created_at":"2024-10-13T11:52:53.292Z","updated_at":"2026-02-16T13:03:41.929Z","avatar_url":"https://github.com/rejunity.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg)\n\n# Rule110 Cellular Automata ASIC for Tiny Tapeout 05\n\nA parallel hardware implementation of the Cellular Automaton in Verilog suitable for ASIC fabrication with [Tiny Tapeout](https://tinytapeout.com/).\n\nThis design executes **256 cells** of an elementary cellular automaton **every cycle** applying [Rule 110](https://en.wikipedia.org/wiki/Rule_110) to all of them **in parallel**.\n\nEach cycle - one evolution step across the whole cellular automaton at 50MHz!\n\n## First success!\n![192 automaton cells](./images/192cells.jpg)\n\n## ASIC area utilisation\nRoughly 128 cells with parallel read/write bus can be placed on a single TinyTapeout tile. Without read/write bus, up to 256 cells fit on a single tile!\n\n**Utilisation** with parallel read/write bus (numbers for 2 tiles):\n* 256 cells, Tile 1x2 :: **64.19%**, 2213 logic of which 258 are Flip Flops, 455 MUX, 276 BUF, [**commit 737130c**](https://github.com/rejunity/tt05-rule110/commit/737130c)\n* 240 cells, Tile 1x2 :: **60.72%**, 2109 logic of which 242 are Flip Flops, 426 MUX, 261 BUF, *commit 1d83f4c*\n* 232 cells, Tile 1x2 :: **59.84%**, 2119 logic of which 234 are Flip Flops, 356 MUX, 281 BUF, *commit 6036188*\n* 224 cells, Tile 1x2 :: **57.19%**, 2054 logic of which 226 are Flip Flops, 272 MUX, 322 BUF, *commit 34538b6*\n* 128 cells, Tile 1x2 :: **31.81%**, 1107 logic of which 130 are Flip Flops, 180 MUX, 128 BUF, *commit 89b27ec*\n*  64 cells, Tile 1x2 :: **15.85%**,  567 logic of which  66 are Flip Flops, 100 MUX,  72 BUF, *commit b9ad400*\n\n**Utilisation** without parallel read/write bus (numbers for 1 tile):\n* 128 cells, Tile 1x1 :: **34.56%**, 713 logic of which 129 are Flip Flops, **commit 4254a88**\n*  32 cells, Tile 1x1 :: **10.49%**, 232 logic of which  33 are Flip Flops, *commit e650da8*\n\n## ASIC fitting 256 automaton cells, **64.19%** of the chip is utilised by logic\n![GDS render with 256 automaton cells](./images/gds_tile1x2_256cells_commit_737130c.png)\n\n## TODO: compare performance with CPU\n\nNot validated yet, but intuition says performance of this ASIC @ 50Mhz should be comparable with a single CPU core @ 1Ghz running AVX SIMD implementation of a Rule 110.\n\n## Interesting facts about Rule 110\n\nRule 110 exhibits complex behavior on the boundary **between stability and chaos**. It could be explored for pseudo random number generator and data compression.\n\n[**Gliders**](https://en.wikipedia.org/wiki/Glider_(Conway%27s_Game_of_Life)) - periodic structures with complex behaviour, universal computation and self-reproduction can be implemented with Rule 110.\n\n[**Turing complete**](https://en.wikipedia.org/wiki/Turing_completeness) - with a particular repeating background pattern Rule 110 is known to be Turing complete.\nThis implies that, in principle, **any** calculation or computer program can be simulated using such automaton!\n\n[**Recurrent Neural Networks**](https://en.wikipedia.org/wiki/Recurrent_neural_network) - it can be shown that one dimensional Cellular Automaton is equivalent to a small **Recurrent Convolutional** Neural Network with [**Step activation**](https://en.wikipedia.org/wiki/Heaviside_step_function) funcion where neuron activations represent the state of the cells. Given the proof of Turing completness for Rule 110 and its complexity of behaviors, Cellular Automaton might be an interesting tool to model more advanced dynamics of Recurrrent nueral networks.\n\nAn example of an interesting pattern developing after a couple hundred iterations:\n```\n▓ ▓▓▓▓▓▓ ▓▓   ▓▓▓   ▓▓ ▓    ▓▓▓▓▓▓▓  ▓   ▓▓ ▓  ▓▓▓▓   ▓  ▓▓ ▓▓▓▓▓\n▓▓▓    ▓▓▓▓  ▓▓ ▓  ▓▓▓▓▓   ▓▓     ▓ ▓▓  ▓▓▓▓▓ ▓▓  ▓  ▓▓ ▓▓▓▓▓   ▓\n▓ ▓   ▓▓  ▓ ▓▓▓▓▓ ▓▓   ▓  ▓▓▓    ▓▓▓▓▓ ▓▓   ▓▓▓▓ ▓▓ ▓▓▓▓▓   ▓  ▓▓\n▓▓▓  ▓▓▓ ▓▓▓▓   ▓▓▓▓  ▓▓ ▓▓ ▓   ▓▓   ▓▓▓▓  ▓▓  ▓▓▓▓▓▓   ▓  ▓▓ ▓▓▓\n  ▓ ▓▓ ▓▓▓  ▓  ▓▓  ▓ ▓▓▓▓▓▓▓▓  ▓▓▓  ▓▓  ▓ ▓▓▓ ▓▓    ▓  ▓▓ ▓▓▓▓▓  \n ▓▓▓▓▓▓▓ ▓ ▓▓ ▓▓▓ ▓▓▓▓      ▓ ▓▓ ▓ ▓▓▓ ▓▓▓▓ ▓▓▓▓   ▓▓ ▓▓▓▓▓   ▓  \n▓▓     ▓▓▓▓▓▓▓▓ ▓▓▓  ▓     ▓▓▓▓▓▓▓▓▓ ▓▓▓  ▓▓▓  ▓  ▓▓▓▓▓   ▓  ▓▓ ▓\n▓▓    ▓▓      ▓▓▓ ▓ ▓▓    ▓▓       ▓▓▓ ▓ ▓▓ ▓ ▓▓ ▓▓   ▓  ▓▓ ▓▓▓▓▓\n ▓   ▓▓▓     ▓▓ ▓▓▓▓▓▓   ▓▓▓      ▓▓ ▓▓▓▓▓▓▓▓▓▓▓▓▓▓  ▓▓ ▓▓▓▓▓    \n▓▓  ▓▓ ▓    ▓▓▓▓▓    ▓  ▓▓ ▓     ▓▓▓▓▓            ▓ ▓▓▓▓▓   ▓   ▓\n▓▓ ▓▓▓▓▓   ▓▓   ▓   ▓▓ ▓▓▓▓▓    ▓▓   ▓           ▓▓▓▓   ▓  ▓▓  ▓▓\n ▓▓▓   ▓  ▓▓▓  ▓▓  ▓▓▓▓▓   ▓   ▓▓▓  ▓▓          ▓▓  ▓  ▓▓ ▓▓▓ ▓▓ \n▓▓ ▓  ▓▓ ▓▓ ▓ ▓▓▓ ▓▓   ▓  ▓▓  ▓▓ ▓ ▓▓▓         ▓▓▓ ▓▓ ▓▓▓▓▓ ▓▓▓▓▓\n ▓▓▓ ▓▓▓▓▓▓▓▓▓▓ ▓▓▓▓  ▓▓ ▓▓▓ ▓▓▓▓▓▓▓ ▓        ▓▓ ▓▓▓▓▓▓   ▓▓▓    \n▓▓ ▓▓▓        ▓▓▓  ▓ ▓▓▓▓▓ ▓▓▓     ▓▓▓       ▓▓▓▓▓    ▓  ▓▓ ▓   ▓\n▓▓▓▓ ▓       ▓▓ ▓ ▓▓▓▓   ▓▓▓ ▓    ▓▓ ▓      ▓▓   ▓   ▓▓ ▓▓▓▓▓  ▓▓\n   ▓▓▓      ▓▓▓▓▓▓▓  ▓  ▓▓ ▓▓▓   ▓▓▓▓▓     ▓▓▓  ▓▓  ▓▓▓▓▓   ▓ ▓▓ \n  ▓▓ ▓     ▓▓     ▓ ▓▓ ▓▓▓▓▓ ▓  ▓▓   ▓    ▓▓ ▓ ▓▓▓ ▓▓   ▓  ▓▓▓▓▓ \n ▓▓▓▓▓    ▓▓▓    ▓▓▓▓▓▓▓   ▓▓▓ ▓▓▓  ▓▓   ▓▓▓▓▓▓▓ ▓▓▓▓  ▓▓ ▓▓   ▓ \n▓▓   ▓   ▓▓ ▓   ▓▓     ▓  ▓▓ ▓▓▓ ▓ ▓▓▓  ▓▓     ▓▓▓  ▓ ▓▓▓▓▓▓  ▓▓▓\n ▓  ▓▓  ▓▓▓▓▓  ▓▓▓    ▓▓ ▓▓▓▓▓ ▓▓▓▓▓ ▓ ▓▓▓    ▓▓ ▓ ▓▓▓▓    ▓ ▓▓  \n▓▓ ▓▓▓ ▓▓   ▓ ▓▓ ▓   ▓▓▓▓▓   ▓▓▓   ▓▓▓▓▓ ▓   ▓▓▓▓▓▓▓  ▓   ▓▓▓▓▓ ▓\n▓▓▓▓ ▓▓▓▓  ▓▓▓▓▓▓▓  ▓▓   ▓  ▓▓ ▓  ▓▓   ▓▓▓  ▓▓     ▓ ▓▓  ▓▓   ▓▓▓\n   ▓▓▓  ▓ ▓▓     ▓ ▓▓▓  ▓▓ ▓▓▓▓▓ ▓▓▓  ▓▓ ▓ ▓▓▓    ▓▓▓▓▓ ▓▓▓  ▓▓  \n  ▓▓ ▓ ▓▓▓▓▓    ▓▓▓▓ ▓ ▓▓▓▓▓   ▓▓▓ ▓ ▓▓▓▓▓▓▓ ▓   ▓▓   ▓▓▓ ▓ ▓▓▓  \n ▓▓▓▓▓▓▓   ▓   ▓▓  ▓▓▓▓▓   ▓  ▓▓ ▓▓▓▓▓     ▓▓▓  ▓▓▓  ▓▓ ▓▓▓▓▓ ▓  \n▓▓     ▓  ▓▓  ▓▓▓ ▓▓   ▓  ▓▓ ▓▓▓▓▓   ▓    ▓▓ ▓ ▓▓ ▓ ▓▓▓▓▓   ▓▓▓ ▓\n▓▓    ▓▓ ▓▓▓ ▓▓ ▓▓▓▓  ▓▓ ▓▓▓▓▓   ▓  ▓▓   ▓▓▓▓▓▓▓▓▓▓▓▓   ▓  ▓▓ ▓▓▓\n ▓   ▓▓▓▓▓ ▓▓▓▓▓▓  ▓ ▓▓▓▓▓   ▓  ▓▓ ▓▓▓  ▓▓          ▓  ▓▓ ▓▓▓▓▓  \n▓▓  ▓▓   ▓▓▓    ▓ ▓▓▓▓   ▓  ▓▓ ▓▓▓▓▓ ▓ ▓▓▓         ▓▓ ▓▓▓▓▓   ▓ ▓\n▓▓ ▓▓▓  ▓▓ ▓   ▓▓▓▓  ▓  ▓▓ ▓▓▓▓▓   ▓▓▓▓▓ ▓        ▓▓▓▓▓   ▓  ▓▓▓▓\n ▓▓▓ ▓ ▓▓▓▓▓  ▓▓  ▓ ▓▓ ▓▓▓▓▓   ▓  ▓▓   ▓▓▓       ▓▓   ▓  ▓▓ ▓▓   \n▓▓ ▓▓▓▓▓   ▓ ▓▓▓ ▓▓▓▓▓▓▓   ▓  ▓▓ ▓▓▓  ▓▓ ▓      ▓▓▓  ▓▓ ▓▓▓▓▓▓  ▓\n▓▓▓▓   ▓  ▓▓▓▓ ▓▓▓     ▓  ▓▓ ▓▓▓▓▓ ▓ ▓▓▓▓▓     ▓▓ ▓ ▓▓▓▓▓    ▓ ▓▓\n   ▓  ▓▓ ▓▓  ▓▓▓ ▓    ▓▓ ▓▓▓▓▓   ▓▓▓▓▓   ▓    ▓▓▓▓▓▓▓   ▓   ▓▓▓▓ \n  ▓▓ ▓▓▓▓▓▓ ▓▓ ▓▓▓   ▓▓▓▓▓   ▓  ▓▓   ▓  ▓▓   ▓▓     ▓  ▓▓  ▓▓  ▓ \n ▓▓▓▓▓    ▓▓▓▓▓▓ ▓  ▓▓   ▓  ▓▓ ▓▓▓  ▓▓ ▓▓▓  ▓▓▓    ▓▓ ▓▓▓ ▓▓▓ ▓▓ \n▓▓   ▓   ▓▓    ▓▓▓ ▓▓▓  ▓▓ ▓▓▓▓▓ ▓ ▓▓▓▓▓ ▓ ▓▓ ▓   ▓▓▓▓▓ ▓▓▓ ▓▓▓▓▓\n```\n\n## How to use the chip once it is done?\n\n### A description of I/O pins\n| INPUTs             | OUTPUTSs          | BIDIRECTIONAL I/O                    |\n| ------------------ | ----------------- | ------------------------------------ |\n| write cell 0 state | read cell 0 state | **/WE** - write enable, inverted     |\n| write cell 1 state | read cell 1 state | **/HALT** - pause automata, inverted |\n| write cell 2 state | read cell 2 state | *ADDR#* - cell block address bit 0   |\n| write cell 3 state | read cell 3 state | *ADDR#* - cell block address bit 1   |\n| write cell 4 state | read cell 4 state | *ADDR#* - cell block address bit 2   |\n| write cell 5 state | read cell 5 state | *ADDR#* - cell block address bit 3   |\n| write cell 6 state | read cell 6 state | *ADDR#* - cell block address bit 4   |\n| write cell 7 state | read cell 7 state | none                                 |\n\n### Reset sequence and automatic execution of the automaton\nAfter RESET all cells will be set to 0 except the rightmost that is going to be 1. Automaton will immediately start running.\nAutomaton will produce new state iteration every cycle for all the cells in parallel. Automaton will continue running until\n`halt automata, inverted` pin is pulled low.\n\nThe 10 first iteration of the automaton after **RESET**.\n```\n                                                    ▓\n                                                   ▓▓\n                                                  ▓▓▓\n                                                 ▓▓ ▓\n                                                ▓▓▓▓▓\n                                               ▓▓   ▓\n                                              ▓▓▓  ▓▓\n                                             ▓▓ ▓ ▓▓▓\n                                            ▓▓▓▓▓▓▓ ▓\n        automaton state on the             ▓▓     ▓▓▓\n      10th iteration after RESET  ----\u003e   ▓▓▓    ▓▓ ▓\n```\n\n### Read automaton state\n\nTo read state of the cells, 1) pull `halt automata, inverted` pin low and 2) set the `cell block address` bits.\n\nCells are read in 8 cell blocks and are addressed sequentially from right to left. Adress #0 represents the rightmost 8 cells.\nAdress #1 represents the cells from 16 to 9 on the rights and so forth.\n\n```\n        automaton state on the \n      10th iteration after RESET  ----\u003e   XXX    XX X\n      00000000  ...  00000000000000000000011100001101\n      |      |              |       |       |       |\n      [adr#14]  ...  [addr#3][addr#2][addr#1][addr#0]\n          cells are addressed in blocks of 8 bits\n```\n\n\n\nThe state of the 8 cells in the block will appear on the pins of `output` path once the `cell block address` is set.\n\n```\nTiming diagram\n\nCLK   ___     ___     ___     ___     ___     ___           ___\n   __/   \\___/   \\___/   \\___/   \\___/   \\___/   \\___ ... _/   \\___\n     |       |       |       |       |       |             |\n     |       |       |       |       |       |             |\n\nWRITE  ____                                                 _______\n    \\__HALT__________________________________________ ... _/ \n\nWRITE_______________  ______________  _______________\n   _/ ADDR#0        \\/ ADDR#1       \\/ ADDR#2 \n\nREAD OUTPUT_______         ________        ________\n   ______/00001101\\_______/00000111\\______/00000000\\_  \n              ^                ^\n              |                |\n\t     these are the expected values on\n\t        the 10th cycle after RESET\n\n      ____\n      HALT  - halt automata, inverted\n      ADDR# - cell block address bits 0..4\n\n```\n\n### (Over)write automaton state\n\nTo write state of the cells, 1) pull `halt automata, inverted` pin low, 2) set the `cell block address` bits,\n3) set the new desired cell state on the `input` path pins and 4) finally pull `write enable, inverted` pin low.\n\nCells are updated in 8 cell blocks and are addressed sequentially from right to left. Adress #0 represents the rightmost 8 cells.\nAdress #1 represents the cells from 16 to 9 on the rights and so forth.\n\n```\nTiming diagram\n\nCLK   ___     ___     ___     ___     ___     ___           ___\n   __/   \\___/   \\___/   \\___/   \\___/   \\___/   \\___ ... _/   \\___\n     |       |       |       |       |       |             |\n     |       |       |       |       |       |             |\nWRITE  ____                                                 _______\n    \\__HALT__________________________________________ ... _/ \n\nWRITE_______________  ______________  _______________\n   _/ ADDR#0        \\/ ADDR#1       \\/ ADDR#2\n\nWRITE INPUT_________  ______________  _____________\n   __/ 00000111     \\/ 11100110     \\/ 11010111    \\_\n\nWRITE______  __    ________  __    ________  __    __ ... _________\n           \\_WE___/        \\_WE___/        \\_WE___/\n                 wait 1 cycle    wait 1 cycle\n\n\n               given the values written above\n         the next 12 cycles of automaton execution\n\n      [adr#14]  ...  [addr#3][addr#2][addr#1][addr#0]\n      |      |              |       |       |       |\n      00000000  ...  00000000110101111110011000000111\n                             ▓▓ ▓ ▓▓▓▓▓▓  ▓▓      ▓▓▓\n                            ▓▓▓▓▓▓▓    ▓ ▓▓▓     ▓▓ ▓\n                           ▓▓     ▓   ▓▓▓▓ ▓    ▓▓▓▓▓\n                          ▓▓▓    ▓▓  ▓▓  ▓▓▓   ▓▓   ▓\n                         ▓▓ ▓   ▓▓▓ ▓▓▓ ▓▓ ▓  ▓▓▓  ▓▓\n                        ▓▓▓▓▓  ▓▓ ▓▓▓ ▓▓▓▓▓▓ ▓▓ ▓ ▓▓▓\n                       ▓▓   ▓ ▓▓▓▓▓ ▓▓▓    ▓▓▓▓▓▓▓▓ ▓\n                      ▓▓▓  ▓▓▓▓   ▓▓▓ ▓   ▓▓      ▓▓▓\n                     ▓▓ ▓ ▓▓  ▓  ▓▓ ▓▓▓  ▓▓▓     ▓▓ ▓\n10 cyles later -\u003e   ▓▓▓▓▓▓▓▓ ▓▓ ▓▓▓▓▓ ▓ ▓▓ ▓    ▓▓▓▓▓\n      __                             ____\n      WE   - write enable, inverted, HALT - halt automata, inverted\n      ADDR# - cell block address bits 0..4\n```\n\n## How to build and test design locally?\n\nFollow the instructions from Tiny Tapeout's [Testing Your Design Guide](https://tinytapeout.com/hdl/testing/) and install required packages, first.\n\n```\n    sudo apt install iverilog verilator\n    pip3 install cocotb pytest\n```\n\nNext run `make` from the `\\src` folder. `make` will compile Verilog source and launch `cocotb` test suite.\n\n```\n    cd src\n    make\n```\n\nYou are done! Feel free to experiment with the code!\n\n\n## What is Tiny Tapeout?\n\nTinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.\n\nTo learn more and get started, visit https://tinytapeout.com.\n\n### Resources\n\n- [FAQ](https://tinytapeout.com/faq/)\n- [Digital design lessons](https://tinytapeout.com/digital_design/)\n- [Learn how semiconductors work](https://tinytapeout.com/siliwiz/)\n- [Join the community](https://discord.gg/rPK2nSjxy8)\n\n### What next?\n\n- Submit your design to the next shuttle [on the website](https://tinytapeout.com/#submit-your-design). The closing date is **November 4th**.\n- Edit this [README](README.md) and explain your design, how it works, and how to test it.\n- Share your GDS on Twitter, tag it [#tinytapeout](https://twitter.com/hashtag/tinytapeout?src=hashtag_click) and [link me](https://twitter.com/matthewvenn)!\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frejunity%2Ftt05-rule110","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frejunity%2Ftt05-rule110","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frejunity%2Ftt05-rule110/lists"}