{"id":22177150,"url":"https://github.com/rejunity/tt10-ternary-dot-product","last_synced_at":"2026-02-14T20:35:51.222Z","repository":{"id":263678070,"uuid":"891136967","full_name":"rejunity/tt10-ternary-dot-product","owner":"rejunity","description":"Ternary 128-element Dot Product (Analysis of the silicon area)","archived":false,"fork":false,"pushed_at":"2024-12-09T08:57:13.000Z","size":55,"stargazers_count":1,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-10-08T07:28:33.765Z","etag":null,"topics":["asic","neuromorphic-hardware"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rejunity.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2024-11-19T19:44:31.000Z","updated_at":"2024-12-09T08:57:16.000Z","dependencies_parsed_at":"2024-12-08T12:27:21.670Z","dependency_job_id":"10e2f6ff-22e9-4f03-baa5-483e37f2c666","html_url":"https://github.com/rejunity/tt10-ternary-dot-product","commit_stats":null,"previous_names":["rejunity/tt10-fractal-neural-net","rejunity/tt10-ternary-dot-product"],"tags_count":0,"template":false,"template_full_name":"TinyTapeout/tt10-verilog-template","purl":"pkg:github/rejunity/tt10-ternary-dot-product","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2Ftt10-ternary-dot-product","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2Ftt10-ternary-dot-product/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2Ftt10-ternary-dot-product/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2Ftt10-ternary-dot-product/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rejunity","download_url":"https://codeload.github.com/rejunity/tt10-ternary-dot-product/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rejunity%2Ftt10-ternary-dot-product/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29455360,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-14T15:52:44.973Z","status":"ssl_error","status_checked_at":"2026-02-14T15:52:11.208Z","response_time":53,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","neuromorphic-hardware"],"created_at":"2024-12-02T08:25:54.149Z","updated_at":"2026-02-14T20:35:51.207Z","avatar_url":"https://github.com/rejunity.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg)\n\n# Large (128 element) ternary dot product (synaptic tree in a silicon neuron)\n\nGoal of this project is to measure and analyse the scaling of the silicon area needed for large ternary dot product area.\nThis is part of a larger work to explore various architectures for Neural Networks on Chip.\n\nFor more information read the [documentation](docs/info.md).\n\n### Ternary dot product\n\n$$y=\\sum_{i=1}^{N} {\\color{Red} A_{i}}\\times {\\color{Green} B_{i}},\n\\quad\n{\\color{Red} A } \\in -1, 0, 1\n\\quad\n{\\color{Green} B } \\in 0, 1 $$\n\n### Performance\n\n**128** element dot-product is computed **each cycle**. At a nominal ASIC frequency of **50 MHz** this design achieves a performance of `6.4 Giga OP/s`.\n\n### Silicon area\n\n| Vector size | Adder tree depth | Output type | # of logic cells | Total # of cells | Wire length (um) | Dimensions (um) | Area (um\u003csup\u003e2\u003c/sup\u003e) | Tiles |\n|-------------|------------------|-------------|------------------|------------------|-------------|------------|------|-------|\n| 1       | - | 2-bit signed |    2|  32|  215|  18 x 11 |  198 um\u003csup\u003e2\u003c/sup\u003e | 0.9%|  \n| 2       | 1 | 3-bit signed |   10|  44|  395|  45 x 8  |  360 um\u003csup\u003e2\u003c/sup\u003e | 1.6%| \n| 4       | 2 | 4-bit signed |   31|  77|  757|  60 x 11 |  660 um\u003csup\u003e2\u003c/sup\u003e | 3.8%|\n||||||||\n| 32      | 5 | 7-bit signed |  336| 508|  9982| 112 x 70 | 7840 um\u003csup\u003e2\u003c/sup\u003e | 36%|\n| 64      | 6 | 8-bit signed |  737|1073| 23329| 160 x 86 |13760 um\u003csup\u003e2\u003c/sup\u003e | 75%|\n| 128*    | 7 | 9-bit signed | 1472|2121| 59822| 112 x 200|**22400 um\u003csup\u003e2\u003c/sup\u003e** | **143%**|\n| 256     | 8 |10-bit signed | 2941|4207|151707| 320 x 112|35840 um\u003csup\u003e2\u003c/sup\u003e | 269%|\n\n*) *Version taped out with TinyTapeout 10*\n\n\n### Comparison betweeen adder-tree versions\n\n| Type                              | Tiles | Wire length (um) | Setup Worst Slack | Setup Slack (Typical) | fMax |\n|-----------------------------------|-------|------------------|-------------------|---------|-|\n| Naive `v[0]+v[1]+v[2]+ ...`   | 38.395 % | 12040 |\t7.3ns |\t13.48ns | 153 MHz |\n| Adder tree                        |\t38.466 % | 11425 | 7.3ns  | 13.45ns | 152 MHz |\n| Logic, carry save adder           | 38.136 % | 10931 | 6.9ns  | 13.41ns | 151 MHz |\n| **HA/FA cells**, carry save adder | 28.712 % | 9164  | **3.5ns** | 12.24ns | **129 MHz** |\n\nNote that there is no significant area difference between various approaches **unless** sky130 [HA/FA cells](https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_hd/cells/fa/README.html) are used!\n\n\n### Physical layout for a 128 element dot product\n![128synapses_1x2tiles_layout](https://github.com/user-attachments/assets/992c77d7-3006-492a-9d75-d1a13e4c0221)\n_Left:_ **blue cells** - compute, **white cells** - ternary vector storage \\\n_Right:_ **wires** connecting cells\n\n### Physical layout for a 32 element dot product\n![32synapses_1tile_layout](https://github.com/user-attachments/assets/ecb97759-9543-4f86-af8d-4a06ad97a2fc)\n**blue cells** - compute, **white cells** - ternary vector storage\n\n# How to test?\nRead the project's [documentation](docs/info.md).\n\n# What is Tiny Tapeout?\n\nTiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.\n\nTo learn more and get started, visit https://tinytapeout.com.\n\n- [FAQ](https://tinytapeout.com/faq/)\n- [Digital design lessons](https://tinytapeout.com/digital_design/)\n- [Learn how semiconductors work](https://tinytapeout.com/siliwiz/)\n- [Join the community](https://tinytapeout.com/discord)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frejunity%2Ftt10-ternary-dot-product","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frejunity%2Ftt10-ternary-dot-product","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frejunity%2Ftt10-ternary-dot-product/lists"}