{"id":13417017,"url":"https://github.com/rggen/rggen","last_synced_at":"2026-01-07T08:10:04.650Z","repository":{"id":37788744,"uuid":"180550709","full_name":"rggen/rggen","owner":"rggen","description":"Code generation tool for configuration and status registers","archived":false,"fork":false,"pushed_at":"2023-12-17T14:24:40.000Z","size":509,"stargazers_count":257,"open_issues_count":12,"forks_count":36,"subscribers_count":14,"default_branch":"master","last_synced_at":"2023-12-17T15:29:54.936Z","etag":null,"topics":["amba","apb","asic","axi","csr","eda","fpga","ral","register-descriptions","rtl","soc","systemverilog","uvm","uvm-ral-model","uvm-register-model","verilog","vhdl","wiki-documents","wishbone-bus"],"latest_commit_sha":null,"homepage":"","language":"Ruby","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rggen.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":".github/FUNDING.yml","license":"LICENSE","code_of_conduct":"CODE_OF_CONDUCT.md","threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null},"funding":{"github":["taichi-ishitani"],"ko_fi":"taichi730"}},"created_at":"2019-04-10T09:41:17.000Z","updated_at":"2024-07-20T17:00:39.400Z","dependencies_parsed_at":"2023-02-01T03:00:25.504Z","dependency_job_id":"27c1af98-221a-4d89-a72d-1a779858f361","html_url":"https://github.com/rggen/rggen","commit_stats":{"total_commits":325,"total_committers":4,"mean_commits":81.25,"dds":"0.043076923076923124","last_synced_commit":"e58520b909d90c52e4db2c2c09c18a378ed1384d"},"previous_names":[],"tags_count":44,"template":null,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rggen%2Frggen","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rggen%2Frggen/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rggen%2Frggen/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rggen%2Frggen/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rggen","download_url":"https://codeload.github.com/rggen/rggen/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243671566,"owners_count":20328635,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["amba","apb","asic","axi","csr","eda","fpga","ral","register-descriptions","rtl","soc","systemverilog","uvm","uvm-ral-model","uvm-register-model","verilog","vhdl","wiki-documents","wishbone-bus"],"created_at":"2024-07-30T22:00:31.230Z","updated_at":"2026-01-07T08:10:04.620Z","avatar_url":"https://github.com/rggen.png","language":"Ruby","funding_links":["https://github.com/sponsors/taichi-ishitani","https://ko-fi.com/taichi730","https://ko-fi.com/A0A231E3I"],"categories":["Other Design Automation tools","Ruby","Register Design","Generators","Hardware Verification"],"sub_categories":["Tools"],"readme":"![RgGen](logo/rggen.png)\n\n[![Gem Version](https://badge.fury.io/rb/rggen.svg)](https://badge.fury.io/rb/rggen)\n[![Docker Pulls](https://img.shields.io/docker/pulls/rggendev/rggen-docker?logo=docker)](https://hub.docker.com/r/rggendev/rggen-docker)\n[![Homebrew Formula Downloads](https://img.shields.io/homebrew/installs/dy/rggen?logo=homebrew)](https://formulae.brew.sh/formula/rggen)\n\n[![CI](https://github.com/rggen/rggen/workflows/CI/badge.svg)](https://github.com/rggen/rggen/actions?query=workflow%3ACI)\n[![Maintainability](https://qlty.sh/badges/a82c7d7a-e35c-4425-8d7e-26b3d09f587a/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen)\n[![codecov](https://codecov.io/gh/rggen/rggen/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen)\n[![Discord](https://img.shields.io/discord/1406572699467124806?style=flat\u0026logo=discord)](https://discord.com/invite/KWya83ZZxr)\n\n[![ko-fi](https://www.ko-fi.com/img/githubbutton_sm.svg)](https://ko-fi.com/A0A231E3I)\n\n# RgGen\n\nRgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), C header file, Wiki documents, from human readable register map specifications.\n\nRgGen has following features:\n\n* Generate source files related to CSR from register map specifications\n    * RTL module\n        * SystemVerilog\n        * Verilog\n            * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin\n        * [Veryl](https://veryl-lang.org)\n            * Need [rggen-veryl](https://github.com/rggen/rggen-veryl) plugin\n        * VHDL\n            * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin\n        * Supports standard bus protocols\n            * AMBA APB\n            * AMBA AXI4-Lite\n            * Avalon-MM\n            * Wishbone\n    * UVM register model (UVM RAL/uvm_reg)\n    * C header file\n    * Register map documents written in Markdown\n* Register map specifications can be written in human readable format\n    * Ruby with APIs to describe register map information\n    * YAML\n    * JSON\n    * TOML\n    * Spreadsheet (XLSX, ODS, CSV)\n* Plugin feature\n    * Allow you to customize RgGen for your environment\n        * Add your own special bit field types\n        * Add your own host bus protocol\n\n## Installation\n\n### Ruby\n\nRgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 3.1 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/documentation/installation/).\n\n### Installation Command\n\nRgGen depends on following sub components and other Ruby libraries.\n\n* [rggen-core](https://github.com/rggen/rggen-core)\n* [rggen-default-register-map](https://github.com/rggen/rggen-default-register-map)\n* [rggen-systemverilog](https://github.com/rggen/rggen-systemverilog)\n* [rggen-c-header](https://github.com/rggen/rggen-c-header)\n* [rggen-markdown](https://github.com/rggen/rggen-markdown)\n* [rggen-spreadsheet-loader](https://github.com/rggen/rggen-spreadsheet-loader)\n\nTo install RgGen and the dependencies, use the command below:\n\n```\n$ gem install rggen\n```\n\nRgGen and dependencies will be installed on your system root.\n\nIf you want to install them on other location, you need to specify install path and set `GEM_PATH` and `PATH` environment variables:\n\n```\n$ gem install --install-dir /path/to/your/install/directory rggen\n$ export GEM_PATH=/path/to/your/install/directory\n$ export PATH=$GEM_PATH/bin:$PATH\n```\n\nYou would get the following error message duaring installation if you have the old RgGen (version \u003c 0.9).\n\n```\nERROR:  Error installing rggen:\n        \"rggen\" from rggen-core conflicts with installed executable from rggen\n```\n\nTo resolve the above error, there are three solutions.\nSee [this page](https://github.com/rggen/rggen/wiki/Resolve-Confliction-of-Installed-Executable)\n\n### Docker Image\n\nThe [rggen-docker](https://hub.docker.com/r/rggendev/rggen-docker) is a Docker image to simplify installation and use of RgGen.\nYou can also execute RgGen by using this image:\n\n```\n$ docker run -ti --rm -v ${PWD}:/work --user $(id -u):$(id -g) rggendev/rggen-docker:latest -c config.yml -o out block_0.yml\n```\n\nSee the [rggen-docker repository](https://github.com/rggen/rggen-docker) for further details.\n\n### Homebrew Installation\n\nOn macOS or Linux, if [Homebrew](https://brew.sh) is installed, you can install RgGen with this command:\n\n```\nbrew install rggen\n```\n\nThis will automatically install Ruby if needed, and will provide RgGen itself as well as the [VHDL](https://github.com/rggen/rggen-vhdl), [Verilog](https://github.com/rggen/rggen-verilog), and [Veryl](https://github.com/rggen/rggen-very) plugins.\n\n## Usage\n\nSee [Wiki documents](https://github.com/rggen/rggen/wiki).\n\n## Plugin\n\nRgGen has `plugin` feature to allow your cusomization.\nSee [this Wiki document](https://github.com/rggen/rggen/wiki/Create-Your-Own-Plugin) for futher detals.\n\n## Supported Tools\n\nFollowing EDA tools can accept the generated source files.\n\n* Simulation tools\n    * Synopsys VCS\n    * Cadence Xcelium\n    * Altair DSim\n    * AMD Vivado Simulator\n    * Verilator\n        * Need `-Wno-unoptflat` switch for Verilog RTL\n    * Icarus Verilog\n        * Verilog RTL only\n* Synthesis tools\n    * Synopsys Design Compiler\n    * Altera Quartus\n    * AMD Vivado\n    * [Yosys](http://www.clifford.at/yosys/)\n        * Verilog RTL\n\n## Example\n\nYou can get sample configuration file and register map specification from the [rggen-sample](https://github.com/rggen/rggen-sample) repository.\nThis register map specification is for a UART IP.\n\n* Configuration file\n    * https://github.com/rggen/rggen-sample/blob/master/config.yml\n* Register map specification\n    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.yml\n\nYou can try to use RgGen by uisng these example files. Hit command below:\n\n```\n$ rggen -c config.yml -o out uart_csr.yml\n```\n\n* `-c`: Specify path to your configuration file\n* `-o`: Specify path to the directory where generated files will be written to\n\nThen, generated files will be written to the `out` directory.\n\nIf you want to generate Verilog RTL, Veryl RTL and VHDL RTL then you need to instll optional plugins listed below.\n\n* Verilog writer plugin: [rggen-verilog](https://github.com/rggen/rggen-verilog)\n* Veryl writer plugin: [rggen-veryl](https://github.com/rggen/rggen-veryl)\n* VHDL writer plugin: [rggen-vhdl](https://github.com/rggen/rggen-vhdl)\n\n```\n$ gem install rggen-verilog\n$ gem install rggen-veryl\n$ gem install rggen-vhdl\n```\n\nIn addition, you need to tell RgGen to use these plugins by using the `--plugin` option switch:\n\n```\n$ rggen -c config.yml --plugin rggen-verilog --plugin rggen-veryl --plugin rggen-vhdl uart_csr.yml\n```\n\nRgGen will generate following source files from the [`uart_csr.yml`](https://github.com/rggen/rggen-sample/blob/master/uart_csr.yml) register map specification:\n\n* SystemVerilog RTL\n    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.sv\n    * https://github.com/rggen/rggen-sample/blob/master/uart_csr_rtl_pkg.sv\n* Verilog RTL\n    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.v\n    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.vh\n* Veryl RTL\n    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.veryl\n* VHDL RTL\n    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.vhd\n* UVM register model\n    * https://github.com/rggen/rggen-sample/blob/master/uart_csr_ral_pkg.sv\n* C header file\n    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.h\n* Markdown document\n    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.md\n\n## Contributing\n\nSee [Contributing Guide](CONTRIBUTING.md).\n\n## Contact\n\nFeedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:\n\n* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)\n* [GitHub Discussions](https://github.com/rggen/rggen/discussions)\n* [Discord](https://discord.com/invite/KWya83ZZxr)\n* [Mailing List](https://groups.google.com/d/forum/rggen)\n* [Mail](mailto:rggen@googlegroups.com)\n\n## See Also\n\n* https://github.com/rggen/rggen-core\n* https://github.com/rggen/rggen-default-register-map\n* https://github.com/rggen/rggen-systemverilog\n* https://github.com/rggen/rggen-c-header\n* https://github.com/rggen/rggen-markdown\n* https://github.com/rggen/rggen-spreadsheet-loader\n* https://github.com/rggen/rggen-verilog\n* https://github.com/rggen/rggen-veryl\n* https://github.com/rggen/rggen-vhdl\n* https://github.com/rggen/rggen-docker\n\n## Copyright \u0026 License\n\nCopyright \u0026copy; 2019-2026 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.\n\n## Code of Conduct\n\nEveryone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](CODE_OF_CONDUCT.md).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frggen%2Frggen","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frggen%2Frggen","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frggen%2Frggen/lists"}