{"id":43691245,"url":"https://github.com/rggen/rggen-sample-testbench","last_synced_at":"2026-02-05T03:37:18.171Z","repository":{"id":37782418,"uuid":"197950343","full_name":"rggen/rggen-sample-testbench","owner":"rggen","description":null,"archived":false,"fork":false,"pushed_at":"2026-02-04T00:58:26.000Z","size":728,"stargazers_count":15,"open_issues_count":1,"forks_count":5,"subscribers_count":3,"default_branch":"master","last_synced_at":"2026-02-04T12:57:17.749Z","etag":null,"topics":["systemverilog","uvm","uvm-ral-model","uvm-register-model","verilog","vhdl"],"latest_commit_sha":null,"homepage":"https://github.com/rggen/rggen","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rggen.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2019-07-20T15:44:12.000Z","updated_at":"2026-02-04T00:58:30.000Z","dependencies_parsed_at":"2025-01-16T10:30:52.590Z","dependency_job_id":"13c59ca4-6993-4902-bb3c-7717159d2ee0","html_url":"https://github.com/rggen/rggen-sample-testbench","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/rggen/rggen-sample-testbench","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rggen%2Frggen-sample-testbench","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rggen%2Frggen-sample-testbench/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rggen%2Frggen-sample-testbench/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rggen%2Frggen-sample-testbench/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rggen","download_url":"https://codeload.github.com/rggen/rggen-sample-testbench/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rggen%2Frggen-sample-testbench/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29109304,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-05T03:27:05.906Z","status":"ssl_error","status_checked_at":"2026-02-05T03:26:43.416Z","response_time":65,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["systemverilog","uvm","uvm-ral-model","uvm-register-model","verilog","vhdl"],"created_at":"2026-02-05T03:37:17.570Z","updated_at":"2026-02-05T03:37:18.160Z","avatar_url":"https://github.com/rggen.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RgGen Sample Testbench\n\nThis is an sample testbench to demonstrate integrating UVM RAL model generated by `RgGen` into UVM based testbench.\n\n## Preparation\n\nThis env uses [flgen](https://github.com/pezy-computing/flgen) to generate *.f files which are given to simulator tools.\nTherefore, you need to install the tool before using this env. See its repository for details.\n\n## DUT\n\nIn this testbech, CSR modules generated by `RgGen` are used as DUT and there are three types of DUT:\n\n* DUT with AMBA APB iterface\n    * https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/apb\n* DUT with AMBA AXI4-Lite interface\n    * https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/axi4lite\n* DUT with Avalon-MM interface\n    * https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/avalon\n* DUT with wishbone interface\n    * https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/wishbone\n* DUT with native interface\n    * https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/native\n\n## Sample Testcases\n\nThis testbench inclues three sample testcases invoking pre-defined test sequences.\n\n| Test Name         | Test Sequence                                                                                                                                                  |\n|:------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|\n| ral_hw_reset_test | [uvm_reg_hw_reset_seq](https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_hw_reset_seq-svh.html) |\n| ral_bit_bash_test | [uvm_reg_bit_bash_seq](https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_bit_bash_seq-svh.html) |\n| ral_access_test   | [uvm_reg_access_seq](https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_access_seq-svh.html)     |\n\n## Usage\n\n### Setup\n\nThis testbench depends on some submodules so you need to get them from GitHub repositries.\nTo do this, hit the command below on the root of this repositly.\n\n```\n$ cd rggen-sample-testbench\n$ ./setup_submodules.sh\n```\n\nIf execution of above commands failed you need to get them from GitHub repositlies directly and set some environment variables.\n\n```\n$ git clone https://github.com/taichi-ishitani/tue.git\n$ export TUE_HOME=`pwd`/tue\n$ git clone https://github.com/taichi-ishitani/tvip-common.git\n$ export TVIP_COMMON_HOME=`pwd`/tvip-common\n$ git clone https://github.com/taichi-ishitani/tvip-apb.git\n$ export TVIP_APB_HOME=`pwd`/tvip-apb\n$ git clone https://github.com/taichi-ishitani/tvip-axi.git\n$ export TVIP_APB_HOME=`pwd`/tvip-axi\n$ git clone https://github.com/rggen/rggen-sv-rtl.git\n$ export RGGEN_SV_RTL_ROOT=`pwd`/rggen-sv-rtl\n$ git clone https://github.com/rggen/rggen-sv-ral.git\n$ export RGGEN_SV_RTL_ROOT=`pwd`/rggen-sv-ral\n$ git clone https://github.com/rggen/rggen-verilog-rtl.git\n$ export RGGEN_VERILOG_RTL_ROOT=`pwd`/rggen-verilog-rtl\n$ git clone https://github.com/rggen/rggen-vhdl-rtl.git\n$ export RGGEN_VHDL_RTL_ROOT=`pwd`/rggen-vhdl-rtl\n```\n\n### Run Simulation\n\nSynopsys VCS simulator, Cadence Xcelium simulator, Metrics DSim simulator and AMD Vivado simulator are supported.\n\n1. Move to the work directry\n    * for DUT with AMBA APB interfac\n        * `sim/apb/systemverilog`\n        * `sim/apb/verilog`\n        * `sim/apb/veryl`\n        * `sim/apb/vhdl`\n    * for DUT with AMBA AXI4-Lite interface\n        * `sim/axi4lite/systemverilog`\n        * `sim/axi4lite/verilog`\n        * `sim/axi4lite/veryl`\n        * `sim/axi4lite/vhdl`\n    * for DUT with Avalon-MM interface\n        * `sim/avalon/systemverilog`\n        * `sim/avalon/verilog`\n        * `sim/avalon/veryl`\n        * `sim/avalon/vhdl`\n    * for DUT with wishbone interface\n        * `sim/wishbone/systemverilog`\n        * `sim/wishbone/verilog`\n        * `sim/wishbone/veryl`\n        * `sim/wishbone/vhdl`\n    * for DUT with native interface\n        * `sim/native/systemverilog`\n        * `sim/native/verilog`\n        * `sim/native/veryl`\n        * `sim/native/vhdl`\n\n2. Hit `make` command on the work directry\n\n```\n$ make\n```\n\nBy default, all sample testcases will be execluted by VCS simulator.\nIf you want to use Xcelium, DSim or Vivado simulator, add `SIMULATOR` option to `makefile` command.\n\n* For Xcelium:\n\n```\n$ make SIMULATOR=xcelium\n```\n\n* For DSim\n\n```\n$ make SIMULATOR=dsim\n```\n\n* For Vivado:\n\n```\n$ make SIMULATOR=vivado\n```\n\nIf you want to execute an specific testcase then you need to give its name to `make` command like below.\n\n```\n$ make ral_bit_bash_test\n```\n\nThe `GUI` option is to enable the inteructive debug environment.\nTo invoke the GUI frontend, give this option to `make` command like below.\n\n* Frontend: DVE\n\n```\n$ make ral_bit_bash_test GUI=dve\n```\n\n* Frontend: Verdi\n\n```\n$ make ral_bit_bash_test GUI=verdi\n```\n\n* Frontend: Indago\n\n```\n$ make ral_bit_bash_test SIMULATOR=xcelium GUI=indago\n```\n\n* Frontend: Vivado\n\n```\n$ make ral_bit_bash_test SIMULATOR=vivado GUI=on\n```\n\n## Contact\n\nYou can post your questions, feedbacks, bug reports, etc. by using following ways.\n\n* [GitHub Issue Tracker](https://github.com/rggen/rggen-sample-testbench/issues)\n* [Discord](https://discord.com/invite/KWya83ZZxr)\n* [Mailing List](https://groups.google.com/d/forum/rggen)\n* [Mail](mailto:rggen@googlegroups.com)\n\n## Copyright \u0026 License\n\nCopyright \u0026copy; 2019-2026 Taichi Ishitani. This testbench is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frggen%2Frggen-sample-testbench","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frggen%2Frggen-sample-testbench","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frggen%2Frggen-sample-testbench/lists"}