{"id":15387354,"url":"https://github.com/rhysd/riscv32-cpu-chisel","last_synced_at":"2025-09-03T03:36:37.075Z","repository":{"id":66059633,"uuid":"398720537","full_name":"rhysd/riscv32-cpu-chisel","owner":"rhysd","description":"Learning how to make RISC-V 32bit CPU with Chisel","archived":false,"fork":false,"pushed_at":"2021-09-17T15:10:53.000Z","size":146,"stargazers_count":66,"open_issues_count":1,"forks_count":4,"subscribers_count":4,"default_branch":"main","last_synced_at":"2025-04-15T19:45:54.468Z","etag":null,"topics":["chisel","chisel3","cpu","risc-v"],"latest_commit_sha":null,"homepage":"","language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rhysd.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.txt","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-08-22T05:19:14.000Z","updated_at":"2025-04-12T10:58:12.000Z","dependencies_parsed_at":null,"dependency_job_id":"54fb775c-c467-4e51-85a6-060119a26496","html_url":"https://github.com/rhysd/riscv32-cpu-chisel","commit_stats":{"total_commits":66,"total_committers":3,"mean_commits":22.0,"dds":"0.030303030303030276","last_synced_commit":"8fbcf8d1433092076998a85637368311793844af"},"previous_names":[],"tags_count":0,"template":false,"template_full_name":"chipsalliance/chisel-template","purl":"pkg:github/rhysd/riscv32-cpu-chisel","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rhysd%2Friscv32-cpu-chisel","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rhysd%2Friscv32-cpu-chisel/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rhysd%2Friscv32-cpu-chisel/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rhysd%2Friscv32-cpu-chisel/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rhysd","download_url":"https://codeload.github.com/rhysd/riscv32-cpu-chisel/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rhysd%2Friscv32-cpu-chisel/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":273386175,"owners_count":25096242,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-09-03T02:00:09.631Z","response_time":76,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel","chisel3","cpu","risc-v"],"created_at":"2024-10-01T14:53:42.456Z","updated_at":"2025-09-03T03:36:37.035Z","avatar_url":"https://github.com/rhysd.png","language":"Scala","funding_links":[],"categories":[],"sub_categories":[],"readme":"RISC-V 32bit CPU written in Chisel\n==================================\n[![CI][ci-badge]][ci]\n\n[RISC-V][riscv] 32bit CPU written in [Chisel][chisel]. This project is for my learning purpose to understand how to design/implement\nhardware with Chisel and what RISC-V architecture is. Working in progress.\n\n## References\n\n- RISC-VとChiselで学ぶ はじめてのCPU自作: https://gihyo.jp/book/2021/978-4-297-12305-5\n  -  'Introduction to making your own CPU with RISC-V and Chisel' Japanese book\n- Chisel API Document: https://www.chisel-lang.org/api/latest/chisel3/index.html\n- RISC-V Spec: https://riscv.org/technical/specifications/\n  - https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf\n- Assembly Manual: https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md\n- Reference simulator: https://github.com/riscv/riscv-isa-sim\n  - Proxy kernel: https://github.com/riscv/riscv-pk\n- \"V\" vector extension: https://github.com/riscv/riscv-v-spec\n  - https://github.com/riscv/riscv-v-spec/releases/download/v1.0-rc1/riscv-v-spec-1.0-rc1.pdf\n- GNU toolchain: https://github.com/riscv/riscv-gnu-toolchain\n  - **TODO:** This repository currently refers to `rvv-0.9.x` branch but it should refer to `rvv-intrinsic` branch for RVV v1.0-rc.\n\nThis repository was imported from [chisel-template@f5f33c6](https://github.com/freechipsproject/chisel-template/tree/f5f33c69f04a64531cbdb31581e09b95583fba91).\n\n## Install\n\nClone this repository:\n\n```sh\ngit clone --recursive https://github.com/rhysd/riscv32-cpu-chisel.git\n```\n\nBuild Docker image for RISC-V GNU toolchain and Scala toolchain:\n\n```sh\ndocker build . -t riscv/mycpu\n```\n\nStart an interactive shell with mounting this repository:\n\n```sh\ndocker run -it -v $(pwd):/app riscv/mycpu\n```\n\n## Generate Verilog sources\n\nVerilog sources can be generated from Chisel sources via `sbt run`:\n\n```sh\nmake ./c/fib.hex # Make hex dump of memory image of program to run\nmake verilog MEMORY_HEX_FILE_PATH=./c/fib.hex # Generate Verilog sources\ncat ./verilog/Top.v\n```\n\n## Test\n\n### riscv-tests\n\nTo run all tests in [riscv-tests](https://github.com/riscv/riscv-tests):\n\n```sh\nmake riscv-tests\n```\n\nOutputs of tests are stored in `riscv-tests-results` directory.\n\nTo run a specific test case in riscv-tests (when running `rv32ui-p-addi` test case):\n\n```sh\nmake ./riscv-tests-results/rv32ui-p-addi.out\n```\n\n### C tests\n\nTo run all tests with C sources in [`c/` directory](./c/):\n\n```sh\nmake c-tests\n```\n\nOutputs of tests are stored in `c-tests-results` directory.\n\nTo run a specific test case in c-tests (when running [`fib.c`](./c/fib.c) test case):\n\n```sh\nmake ./c-tests-results/fib.out\n```\n\n### Rust tests\n\nTo run all tests with Rust sources in [`rust/` directory](./rust/):\n\n```sh\nmake rust-tests\n```\n\nOutputs of tests are stored in `rust-tests-results` directory.\n\nTo run a specific test case in rust-tests (when running [`fib`](./rust/src/fib) test case):\n\n```sh\nmake ./rust-tests-results/fib.out\n```\n\n### Run tests with the uploaded Docker image\n\nRun `docker run` with [the uploaded Docker image][docker].\n\n```sh\ndocker run --rm -v $(pwd):/app --workdir /app -t rhysd/riscv-cpu-chisel:latest make riscv-tests\n```\n\n## License\n\nDistributed under [the MIT license](./LICENSE.txt).\n\n[ci-badge]: https://github.com/rhysd/riscv32-cpu-chisel/actions/workflows/ci.yaml/badge.svg\n[ci]: https://github.com/rhysd/riscv32-cpu-chisel/actions/workflows/ci.yaml\n[riscv]: https://riscv.org/\n[chisel]: https://www.chisel-lang.org/\n[docker]: https://hub.docker.com/r/rhysd/riscv-cpu-chisel\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frhysd%2Friscv32-cpu-chisel","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frhysd%2Friscv32-cpu-chisel","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frhysd%2Friscv32-cpu-chisel/lists"}