{"id":15387362,"url":"https://github.com/rhysd/toy-riscv-backend","last_synced_at":"2025-04-15T17:33:54.261Z","repository":{"id":66059675,"uuid":"515381645","full_name":"rhysd/toy-riscv-backend","owner":"rhysd","description":"Toy RISC-V LLVM backend","archived":false,"fork":false,"pushed_at":"2022-08-15T10:40:18.000Z","size":147,"stargazers_count":25,"open_issues_count":0,"forks_count":8,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-03-29T00:33:21.072Z","etag":null,"topics":["llvm","llvm-backend","riscv"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rhysd.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.txt","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-07-19T00:25:25.000Z","updated_at":"2025-02-06T14:24:03.000Z","dependencies_parsed_at":null,"dependency_job_id":"37aa673d-1dbd-4798-99d7-ad450aa5f227","html_url":"https://github.com/rhysd/toy-riscv-backend","commit_stats":{"total_commits":28,"total_committers":1,"mean_commits":28.0,"dds":0.0,"last_synced_commit":"4127e366128cdbc0c4b4854f8f016446a2ac780b"},"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rhysd%2Ftoy-riscv-backend","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rhysd%2Ftoy-riscv-backend/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rhysd%2Ftoy-riscv-backend/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rhysd%2Ftoy-riscv-backend/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rhysd","download_url":"https://codeload.github.com/rhysd/toy-riscv-backend/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":249119088,"owners_count":21215669,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["llvm","llvm-backend","riscv"],"created_at":"2024-10-01T14:53:43.350Z","updated_at":"2025-04-15T17:33:53.974Z","avatar_url":"https://github.com/rhysd.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"Toy RISC-V LLVM Backend\n=======================\n\nYet another RISC-V LLVM Backend. This is a project for learning how LLVM backend works and what RISC-V architecture is\nby reimplementing the official LLVM's RISC-V backend.\n\n## References\n\n- Official RISC-V backend (LLVM 14.0.6): https://github.com/llvm/llvm-project/tree/f28c006a5895fc0e329fe15fead81e37457cb1d1/llvm/lib/Target/RISCV\n- RISC-V specification: https://riscv.org/technical/specifications/\n  - v20191213 (PDF): https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf\n- RISC-V Assembly Manual: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md\n- Writing an LLVM Backend: https://llvm.org/docs/WritingAnLLVMBackend.html\n  - Basic Steps: https://llvm.org/docs/WritingAnLLVMBackend.html#basic-steps\n\n## Getting started\n\nClone this repository:\n\n```sh\ngit clone --recursive https://github.com/rhysd/toy-riscv-backend.git\n```\n\nSetup LLVM:\n\n```sh\ncd /path/to/toy-riscv-backend\n./setup.bash\ncd ./llvm-project/llvm\nmkdir ./build \u0026\u0026 cd ./build\ncmake -G Ninja -DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD=\"X86;TOYRISCV;RISCV\" -DLLVM_ENABLE_PROJECTS=\"clang;libcxx;libcxxabi\" ..\nninja\n```\n\n[setup.bash](./setup.bash) links all sources in [llvm/](./llvm) to [llvm-project/llvm/](./llvm-project/llvm) so that our\nbackend is built as a part of `llc` compiler.\n\nSetup RISC-V toolchain:\n\n```sh\ndocker build . -t riscvback\ndocker run -it --rm -v $(pwd):/app riscvback /bin/bash\n```\n\nRISC-V toolchain like `riscv64-unknown-elf-gcc` or `spike` are available in the Docker container.\n\n## Related projects\n\n- Toy RISC-V 32bit CPU written in Chisel: https://github.com/rhysd/riscv32-cpu-chisel\n\n## Random notes\n\n### How to compile and run C sources with RISCV backend\n\nCompile sources.\n\nSetting triple as `--target=riscv64-unknonw-linux-gnu` is necessary to emit LLVM IR targetting 64bit RISC-V processor.\n`-march` may not be necessary, but ensure that CPU arch is `rv64g`. It emits `source.bc`.\n\n```sh\n./llvm-project/llvm/build/bin/clang --target=riscv64-unknown-linux-gnu -march=rv64g -emit-llvm -c source.c\n```\n\nCompile LLVM bitcode to assembly code.\n\nSet CPU arch to `-march=riscv64`. Default value of `-mcpu` is `generic-v64` so it is not necessary but here we ensure it.\n`-mattr` specifies what CPU excentions can be used. In this example, we enable 'd' extension by adding `+d`.\nIt emits `source.s`.\n\n```sh\n./llvm-project/llvm/build/bin/llc -march=riscv64 -mcpu=generic-rv64 -mattr=+d -filetype=asm source.bc\n```\n\nCheck the generated assembly code. The `.attribute 5` is the attribute representing CPU arch. Check the CPU arch\nsupports all features you need.\n\n```asm\n\t.text\n\t.attribute\t4, 16\n\t.attribute\t5, \"rv64i2p0_f2p0_d2p0\"\n\t.file\t\"source.c\"\n\t.globl\tmain\n\t.p2align\t2\n\t.type\tmain,@function\nmain:\n...\n```\n\nWhen no feature is enabled, the CPU arch will be `rv64i2p0`. If the assembly code tries to use a feature which is not\nenabled by the processor, the following GCC command reports an error like below:\n\n```\nsource.s:10: Error: ilp32d/lp64d ABI can't be used when d extension isn't supported\n```\n\nFinally compile the assembly code to an object file and run it via Spike simulator on Docker container.\n\n```sh\nriscv64-unknown-elf-gcc source.s -lc -o source.o\nspike pk source.o\n```\n\nNote that compiling to an object file from LLVM bitcode via `llc` with `-filetype=obj` does not work.\n\n### How to compile C sources to assembly with our own TOYRISCV backend\n\nCompile to LLVM bitcode using Clang with `riscv64-unknown-elf` target.\n\n```sh\n./llvm-project/llvm/build/bin/clang --target=riscv64-unknown-elf -O3 hello.c -c -emit-llvm -o hello.bc\n```\n\nThen compile the bitcode to RISC-V 64bit assembly using our own TOYRISCV backend.\n\n```sh\n./llvm-project/llvm/build/bin/llc -debug -march=toyriscv64 -filetype=asm hello.bc -o hello.S\n```\n\n## License\n\nThis project is licensed under [the MIT license](./LICENSE.txt).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frhysd%2Ftoy-riscv-backend","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frhysd%2Ftoy-riscv-backend","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frhysd%2Ftoy-riscv-backend/lists"}